Deterministic Latency
Many JESD204 systems contain a variety of data processing units, which operate in different clock domains, leading to indeterminate latency. These latencies will produce random delays during link layer power up, power down, and reset. JESD204A does not provide a method to handle interface delays, whereas JESD204B offers two mechanisms (Subclass 1, Subclass 2) to address the issue of indeterminate latency.
Data Link Delay is defined as:The time difference between the parallel data frames sent from the TX device and the parallel data frames output from the RX device, calculated by the frame clock. The delay is measured in frame clock units, and the smaller the delay, the better. Additionally, auxiliary timing information must be provided during power up, power down, and resynchronization to meet input requirements.
Determined data link delay requires two conditions:
1. In the TX device, ILA (initial lane alignment) must ensure that all lanes start simultaneously, with the start time being the first edge of LMFC after the SYNC rising edge or the set LMFC cycle.
2. In the RX device, incoming data must be buffered to eliminate delays caused by TX SERDES lanes, physical channels, and RX SERDES lanes. Data can be released at the edges of LMFC.
The transmission from the TX device and the release of the buffer from the RX device will be aligned with LMFC, so the fixed data delay is determined by the alignment of the sending and receiving ends’ LMFC.
To better implement a fixed delay protocol, the following three points should be noted:
1. The LMFC cycle must be greater than the data link delay.
2. The time for buffering data in the RX device’s buffer must be greater than the data link delay.
3. The buffer size must be between 1 and K.
The above three points ensure that when the RX buffer releases data, all sent data has already arrived at the RX device.
The final data link delay will equal the buffer size * T.
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