FPGA Clock Constraints (Part 1)
Clock constraint commands in Vivado create_clock create_clock -name <name> -period <period> -waveform {<rise_name> <fall_name> } {get_ports <input_port>} create_clock is used to create the primary clock create_clock -name <clk0> -period <10.000> -waveform {0 5} {get_ports clk0} (default state) create_clock -name <clk1> -period <10.000> -waveform {2 8} {get_ports clk1} create_generated_clock create_generated_clock is used to constrain derived clocks … Read more
