100 Questions on Embedded Hardware and Electronics – Bus Communication Protocols (Detailed Answers for Beginners)

1. Briefly describe your understanding of UART bus

UART (Universal Asynchronous Receiver-Transmitter) is the most commonly used serial communication bus in embedded systems, characterized by its “asynchronous, point-to-point, and easy-to-use” nature:

• Communication method: Asynchronous communication, no clock signal synchronization is required, communication is achieved through agreed baud rate and data format.

• Hardware interface: Requires at least 2 wires (TX for transmission, RX for reception), full-duplex communication (can send and receive simultaneously), and in some scenarios, GND (common ground) is needed to ensure signal stability.

• Data format: Each data frame includes a start bit (1 bit low level), data bits (5-9 bits, commonly 8 bits), parity bit (0-1 bit, odd/even/no parity), and stop bits (1-2 bits, commonly 1 bit).

• Advantages: Simple hardware, low cost, easy wiring, suitable for short distances (from a few meters to tens of meters) and medium-low speed (baud rate ≤ 115200 bps) communication.

• Disadvantages: Does not support multiple slave devices (point-to-point communication), weak anti-interference capability (single-ended signal transmission), and baud rate error must not exceed 5% (otherwise communication fails).

• Application scenarios: Communication between microcontrollers and PCs, sensor data transmission, module control (e.g., Bluetooth modules, GPS modules).

2. The working principle of I2C bus

I2C (Inter-Integrated Circuit) is a two-wire synchronous serial bus, characterized by its “multi-master, multi-slave, fewer wires, and ease of use”:

• Hardware interface: Requires only 2 wires, SDA (serial data line, bidirectional) and SCL (serial clock line, bidirectional), all devices share the bus, and pull-up resistors (usually 4.7kΩ-10kΩ) to the power supply are needed.
• Communication principle:

1. The master device initiates communication: sends a start signal (SDA changes from high to low, SCL is high), then sends the slave device address (7-bit or 10-bit) + read/write control bit (R/W).
2. The slave device responds: the selected slave device sends an acknowledgment signal (ACK, SDA pulled low), while unselected devices remain in high-impedance state.
3. Data transmission: The master device provides the clock through SCL, during the high level of SCL, the signal on SDA is stable (data valid), and during the low level, SDA can change (preparing the next data bit), each transmission consists of 8 bits of data, followed by receiving an acknowledgment.
4. Communication ends: The master device sends a stop signal (SDA changes from low to high, SCL is high), releasing the bus.

• Advantages: Supports multi-master and multi-slave (up to 127 devices with 7-bit addresses), simple wiring, suitable for short distances (a few meters), and medium-low speed (100kbps-400kbps) communication.
• Disadvantages: Moderate transmission rate, general anti-interference capability (requires good wiring).

3. How to distinguish between start and stop signals when using I2C bus communication?

The start and stop signals of the I2C bus are generated by the master device, distinguished by the level changes of SDA and SCL, with the core being “SCL high level when SDA changes”:

• Start signal (S): When SCL is high, SDA quickly changes from high to low (high→low), indicating the start of communication. Key: SCL must be high for the SDA change to be valid, which is the only identifier for the start signal.

• Stop signal (P): When SCL is high, SDA quickly changes from low to high (low→high), indicating the end of communication. Key: Similarly, SCL must be high, and the reverse change of SDA is the identifier for the stop signal.

• Supplement: When SCL is low, the level changes of SDA are not considered start or stop signals, only used to prepare the next data bit.

4. Discuss your understanding of SPI bus

SPI (Serial Peripheral Interface) is a synchronous serial communication bus, characterized by its “high speed, full duplex, and multi-slave”:

• Hardware interface: 4 wires (standard), SCLK (serial clock, output from master), MOSI (master out slave in, master→slave), MISO (master in slave out, slave→master), CS (chip select, output from master, low level selects the slave).

• Communication method: Synchronous communication, the master device provides the clock through SCLK, all data transmissions are synchronized to SCLK, the CS line is used to select the currently communicating slave device (when there are multiple slaves, multiple CS lines or daisy chaining is needed).
• Data transmission:

1. The master device pulls down the target slave’s CS line (selecting it).
2. The master device outputs the clock through SCLK, on the rising or falling edge of the clock, the master device sends data through MOSI, and the slave device returns data through MISO (full duplex, simultaneous send and receive).
3. After transmission ends, the master device pulls the CS line high, releasing the slave.

• Advantages: High transmission rate (up to tens of Mbps), full duplex communication, strong anti-interference capability (differential clock synchronization), supports multiple slave devices.
• Disadvantages: More hardware lines than I2C, does not support multiple master devices (default master-slave structure), wiring needs to pay attention to clock synchronization.
• Application scenarios: High-speed data transmission (e.g., Flash memory, ADC chips, displays), industrial control modules.

5. The four operating modes of SPI bus

The four operating modes of the SPI bus are determined by the “clock polarity (CPOL)” and “clock phase (CPHA)”, with the core being “the clock edge for data sampling and sending”:

• Clock polarity (CPOL): The level of SCLK in idle state (when no data is transmitted). When CPOL=0, SCLK is idle low; when CPOL=1, SCLK is idle high.

• Clock phase (CPHA): The clock edge for data sampling. When CPHA=0, sampling occurs on the first clock edge (rising or falling); when CPHA=1, sampling occurs on the second clock edge.
• Details of the four modes:

1. Mode 0 (CPOL=0, CPHA=0): SCLK idle low, data sampled on the rising edge, data sent on the falling edge (most commonly used).
2. Mode 1 (CPOL=0, CPHA=1): SCLK idle low, data sampled on the falling edge, data sent on the rising edge.
3. Mode 2 (CPOL=1, CPHA=0): SCLK idle high, data sampled on the falling edge, data sent on the rising edge.
4. Mode 3 (CPOL=1, CPHA=1): SCLK idle high, data sampled on the rising edge, data sent on the falling edge.

• Key: The master and slave devices must be set to the same operating mode; otherwise, data transmission errors will occur (sampling and sending edges do not match).

6. What issues need to be considered when using I2C bus?

When using the I2C bus, focus on “bus conflicts, timing matching, and anti-interference” to avoid communication failures:

• Address conflict: When there are multiple slave devices, ensure each slave device address is unique (7-bit address allows up to 127 devices), which can be modified through hardware address pins (e.g., A0/A1/A2) to avoid conflicts.

• Pull-up resistor selection: SDA and SCL need to connect to pull-up resistors of 4.7kΩ-10kΩ; if the resistor is too large, it will cause the signal rise time to be too slow, and if too small, it will increase bus power consumption, requiring adjustment based on bus length and number of devices.

• Timing matching: The SCL clock frequency of the master device must not exceed the maximum supported frequency of the slave device (e.g., standard I2C 100kbps, fast I2C 400kbps); otherwise, the slave device cannot correctly sample data.

• Bus capacitance limit: The total parasitic capacitance of all devices on the bus must not exceed 400pF; otherwise, signal distortion may occur, which can be resolved by shortening the bus length or reducing the number of devices.

• Anti-interference: SDA and SCL lines should be as short and parallel as possible, away from high-frequency signal lines (e.g., clock lines), and use shielded cables if necessary to avoid electromagnetic interference causing data errors.

• Acknowledgment signal handling: The master device needs to detect the ACK signal from the slave device; if there is no ACK, it needs to resend or terminate communication to prevent communication deadlock.

7. In UART communication, what are the roles of baud rate, data bits, stop bits, and parity bits (odd/even/no parity)?

The core of UART communication is “agreeing on the same data format”; all four parameters are essential:

• Baud rate: Measured in bps (bits per second), it indicates the number of binary bits transmitted per second, serving as a communication speed indicator. The master and slave devices must set the same baud rate (error ≤ 5%); otherwise, data sampling errors will occur. Common baud rates include: 9600bps, 19200bps, 115200bps (most commonly used).

• Data bits: The number of valid data bits included in each data frame, commonly 8 bits (standard ASCII code), but can also choose 5-9 bits. The more data bits, the larger the amount of information transmitted in a single transmission, suitable for scenarios requiring large data transmission.

• Stop bits: The end identifier of each data frame, commonly 1 bit, but can also choose 1.5 bits or 2 bits. The stop bit is used to synchronize the next transmission; the more bits, the stronger the anti-interference capability, but the lower the transmission efficiency.
• Parity bit: A redundant bit used to detect errors in data transmission, divided into three types:

1. Odd parity: The total number of data bits + parity bit is odd (e.g., 8 data bits 10101010, parity bit is 1, total is 9 (odd)).
2. Even parity: The total number of data bits + parity bit is even (e.g., in the above example, parity bit is 0, total is 8 (even)).
3. No parity: No parity bit is added, providing the highest transmission efficiency but unable to detect transmission errors, suitable for scenarios with low interference.

8. What is the difference between 7-bit and 10-bit slave device addresses in I2C bus? How to avoid address conflicts among multiple slave devices?

• Difference between 7-bit and 10-bit addresses:

Comparison Dimension	7-bit Address	10-bit Address
Address Range	0000000-1111111 (127 addresses)	0000000000-1111111111 (1024 addresses)
Address Byte	1 byte (first 7 bits address, 8th bit read/write bit)	2 bytes (first 5 bits fixed as 11110, followed by 10-bit address)

Transmission Efficiency	High (sends 1 byte less)	Low (sends 1 extra byte)
Applicable Scenarios	Fewer devices (≤127), regular scenarios	More devices (>127), complex systems

Compatibility

All I2C devices support

Some older devices may not support

• Methods to avoid address conflicts:

1. Preferably use 7-bit addresses, modifying addresses through hardware address pins (A0/A1/A2) (e.g., setting multiple identical address sensors to different addresses).
2. When the number of devices is large, use 10-bit addresses to expand the address space.
3. Software address negotiation: After the master device powers on, scan the bus to assign unique addresses to unallocated slave devices (requires device support for software address configuration).
4. Avoid using reserved addresses (e.g., 7-bit addresses 0000000 (broadcast address), 1111111 (reserved)).

9. What is the clock stretching mechanism in I2C bus? In which scenarios is it suitable for slower responding slave devices?

• Clock stretching mechanism: In the I2C bus, the master device usually controls the SCL clock, but if the slave device needs extra time to process after receiving or sending data (e.g., reading internal registers, preparing data), it can actively pull the SCL line low, keeping the clock low. The master device detects that SCL is pulled low and will pause sending the clock until the slave device releases SCL (pulls it high), at which point the master device continues transmission.

• In simple terms: The slave device “holds” the clock line to “request a delay” from the master device, ensuring it has enough time to process data.
• Applicable scenarios:

1. Low-speed sensors: Such as some temperature sensors, ADC chips, which require a longer time to read data (e.g., tens of μs), need to wait for data preparation to complete through clock stretching.
2. Heavy load on slave devices: When a slave device is handling multiple tasks simultaneously (e.g., receiving data + storing to Flash), it cannot respond in time, and clock stretching is used to avoid data loss.
3. Long-distance communication: When the I2C bus is too long, signal transmission delays can be compensated by clock stretching.

• Note: The master device must support clock stretching functionality (most microcontroller I2C peripherals support it); otherwise, it will ignore the slave device’s stretching signal, leading to communication errors.

10. What are the roles of SCLK (clock), MOSI (master out slave in), MISO (master in slave out), and CS (chip select) lines in SPI bus?

The four lines of the SPI bus have clear roles, and none can be omitted, with the core being “master device controls, slave device responds”:

• SCLK (Serial Clock): The serial clock line, output from the master device, used to synchronize data transmission. The rising or falling edge of the clock is the trigger signal for data sampling and sending, and the clock frequency determines the SPI transmission rate.

• MOSI (Master Out Slave In): The master out slave in line, the channel for data transmission from the master device to the slave device. The master device places data on the MOSI line on the corresponding edge of the clock, and the slave device synchronously samples and receives it.

• MISO (Master In Slave Out): The master in slave out line, the channel for data transmission from the slave device to the master device. The slave device places data on the MISO line on the corresponding edge of the clock, and the master device synchronously samples and receives it (the key to full duplex communication).

• CS (Chip Select): The chip select line, output from the master device, used to select the currently communicating slave device. When multiple slave devices share the SPI bus, the master device pulls down the corresponding slave’s CS line to select it (other slave CS lines are high, in high-impedance state), and after communication ends, the CS line is pulled high to release the slave.

• Supplement: Some simplified SPI circuits may omit the MISO line (only one-way transmission from master to slave) or the CS line (in single slave device scenarios), but standard SPI requires four lines to achieve full duplex, multi-slave communication.

11. In UART communication, why is it necessary to set the same baud rate? What baud rate error will cause communication failure?

• Why the same baud rate is needed: UART is asynchronous communication, with no clock signal synchronization; the master and slave devices can only determine the transmission time of each data bit through the “agreed baud rate” (bit period = 1 / baud rate). For example, at a baud rate of 9600bps, the bit period is about 104μs, and devices sample data every 104μs. If the baud rates are different, the sampling times will not match, leading to data recognition errors (e.g., recognizing 0 as 1 or losing bits).

• Allowed baud rate error range: Typically, the baud rate error must not exceed ±5%; exceeding this will lead to communication failure. For example: if the master device baud rate is 115200bps (bit period 8.68μs) and the slave device baud rate is 120000bps (bit period 8.33μs), the error is about 3.1% (within the allowed range), and communication can proceed normally; if the slave device baud rate is 130000bps (bit period 7.69μs), the error is about 11.3% (exceeding 5%), resulting in garbled data or loss.

• Reason: The UART receiver typically samples at the midpoint of each data bit (most stable); if the error exceeds 5%, the sampling point will deviate from the stable area of the data, leading to sampling errors.

12. Who generates the ACK (acknowledgment) and NACK (non-acknowledgment) signals in the I2C bus? What is their function?

The ACK and NACK signals in the I2C bus are the “confirmation mechanism” for data transmission, ensuring data is correctly received:

• Generating party: The ACK and NACK signals are generated by the “device receiving the data” (when the master device receives, it generates the signal; when the slave device receives, the slave generates the signal). Example 1: The master device sends data to the slave device → the slave generates ACK/NACK after receiving every 8 bits of data. Example 2: The master device reads data from the slave device → the master generates ACK/NACK after receiving every 8 bits of data.

Signal definitions:

1. ACK (acknowledgment): The receiving device pulls SDA low during the 9th clock cycle (after the data bits), indicating that the data has been correctly received, and the sending device can continue transmitting the next byte.
2. NACK (non-acknowledgment): The receiving device keeps SDA high during the 9th clock cycle, indicating that the data was not received (e.g., address error, data overflow) or that the transmission has ended, and the sending device should stop transmitting.

Functions:

1. Confirm successful data transmission, preventing data loss.
2. Notify the sending device whether to continue transmission (ACK continues, NACK stops).
3. The master device can terminate the read operation through the NACK signal (e.g., after reading the target data, send NACK + stop signal).

13. What is the “daisy chain” connection method in SPI bus? What are the advantages and disadvantages compared to the “multi-chip select” method?

• Daisy chain connection method: Multiple slave devices are connected in series on the SPI bus, with the MISO pin of the previous slave device connected to the MOSI pin of the next slave device, and the MISO pin of the last slave device connected to the MISO pin of the master device. All slave devices share the SCLK and CS lines (only 1 CS line is needed). During communication: the data sent by the master device passes through each slave device in turn, and the response data from the last slave device is returned in sequence, achieving communication with multiple slave devices.

• Comparison with the multi-chip select method (one CS line for each slave device):

Comparison Dimension	Daisy Chain Method	Multi-Chip Select Method
Number of CS Lines	1 (saves IO ports)	N (N is the number of slave devices, occupies more IO ports)
Transmission Efficiency	Low (data must pass through all slave devices, efficiency decreases as the number of slaves increases)	High (directly selects the target slave device, communicates only with that device)

Wiring Complexity	Simple (no extra CS lines needed, only connect MISO/MOSI in series)	Complex (CS lines need to be wired for each slave device)
Device Control	Can only communicate in sequence, cannot individually select a specific slave device (requires all slaves to cooperate in shifting)	Can individually select any slave device, flexible control

Applicable Scenarios

Many slave devices, low transmission efficiency requirements (e.g., LED matrix, shift registers)

Few slave devices, high transmission efficiency requirements (e.g., Flash, ADC chips)

14. What is the working principle of the CAN bus? How is its “non-destructive bus arbitration” mechanism implemented?

• Working principle: CAN (Controller Area Network) is a differential serial communication bus, characterized by its “multi-master, multi-slave, strong anti-interference, and high reliability”, mainly used in industrial control, automotive electronics, and other scenarios.

1. Hardware interface: Uses differential signal lines (CAN_H and CAN_L), with 120Ω termination resistors at both ends of the bus, all devices are connected in parallel on the bus, and no address allocation is needed (target is identified through data frame ID).
2. Data transmission: Devices send data frames (containing ID, data length, data, and checksum) through the CAN controller, and all devices on the bus receive the data frame, determining whether it is the target device through the ID, while non-target devices ignore the frame.

• Non-destructive bus arbitration mechanism: When multiple master devices send data to the bus simultaneously, they determine priority through ID to avoid data conflicts, and it does not destroy already sent valid data:

1. Bus level rules: The differential level of CAN_H and CAN_L determines the bus state, where dominant level (logic 0) has higher priority than recessive level (logic 1), meaning that as long as one device sends a dominant level, the bus is in a dominant state.
2. Arbitration process: When multiple devices send data frames simultaneously, they compare from the highest bit of the ID: 1. If a device sends a recessive level (1), but detects a dominant level (0) on the bus, it indicates that a higher priority device is sending (lower ID, higher priority), and that device immediately stops sending and switches to receiving state. 2. The device with the highest priority (smallest ID) will continue to send the entire data frame, while other devices will wait for the bus to be free before attempting to send.
3. Core advantage: The arbitration process does not destroy already sent valid data, leading to high bus utilization, suitable for scenarios with high real-time requirements.

15. What is the difference between dominant and recessive levels in the CAN bus? How to determine the bus state through levels?

Difference between dominant and recessive levels: The CAN bus represents logic levels through the differential voltage of CAN_H and CAN_L, with the core being “the presence or absence of differential voltage”:

Level Type	Differential Voltage (CAN_H – CAN_L)	Bus State	Logic Value	Driving Method
Dominant Level	About 2V (e.g., CAN_H=3.5V, CAN_L=1.5V)	Driven (actively driven by a device)	0	Multiple devices can drive simultaneously, dominant has priority

Recessive Level

About 0V (CAN_H=CAN_L=2.5V)

Passive (no device driving, relies on termination resistors)

1

Only when all devices are not driving, the bus is recessive

• Bus state determination:

1. Bus idle: No devices are sending data, the bus is in a recessive state (CAN_H=CAN_L=2.5V), at this time any device can initiate communication.
2. Bus busy: At least one device is sending data, the bus is in a dominant state (CAN_H and CAN_L have a 2V differential), and other devices must wait for the bus to be free before sending.
3. Arbitration state: When both dominant and recessive levels appear on the bus, the dominant level overrides the recessive level, and the arbitration result can be determined through level changes (sustained dominant indicates a high-priority device is sending).

16. What are the requirements for the topology structure (bus type/star type) of the RS-485 bus? What is the role of the termination resistor (120Ω)?

Topology structure requirements: The RS-485 bus is a differential serial communication bus, with the core requirement being to use a “bus-type topology”, and star-type topology is prohibited:

1. Bus-type topology: All devices’ A (+) and B (-) pins are connected in parallel to one A line and one B line, with termination resistors connected at both ends of the bus (the two devices at the farthest distance), and the distance between devices should be as uniform as possible, with the bus length not exceeding about 1200 meters.
2. Star-type topology is prohibited: Star-type topology can lead to severe signal reflection and attenuation, and multiple branch lines can cause signal interference, resulting in reduced communication distance and increased error rates, which cannot be improved even with termination resistors.

• Role of termination resistor (120Ω):

1. Matches the bus characteristic impedance: The characteristic impedance of the RS-485 bus is about 120Ω, and the termination resistor can match the bus impedance, reducing signal reflection (high-frequency signals reflecting at both ends of the bus can cause waveform distortion).
2. Enhances signal integrity: Prevents reflected signals from superimposing on the original signal, leading to the receiving end being unable to correctly identify data, especially in long-distance, high-speed (e.g., above 1Mbps) communication, where termination resistors are essential.
3. Note: Termination resistors should only be connected at both ends of the bus; intermediate devices should not connect them, as this would increase bus load and lead to signal attenuation.

17. What are the differences in hardware connections between half-duplex and full-duplex communication in RS-485 bus? What are the applicable scenarios for each?

• Hardware connection differences: The core difference lies in “the number of data lines” and “transmit/receive control”:

1. Half-duplex communication (most common):

1. Hardware: Requires only 2 differential lines (A line, B line), all devices’ transmit (TX) and receive (RX) ends share the A and B lines through transceivers (e.g., MAX485), requiring one control pin (e.g., DE/RE) to control the transceiver’s transmit/receive state.

2. Connection: The transceiver’s DI (data input) connects to the microcontroller’s TX, RO (data output) connects to the microcontroller’s RX, and the DE and RE pins are shorted and connected to a microcontroller GPIO pin (high level for sending, low level for receiving).2. Full-duplex communication:

• Hardware: Requires 4 differential lines (A+, A-, B+, B-), divided into a transmit channel (A+, A-) and a receive channel (B+, B-), and the transceiver does not require control pins, allowing simultaneous sending and receiving.
• Connection: The transmit channel’s DI connects to TX, and the receive channel’s RO connects to RX, with no additional GPIO control needed.

• Applicable scenarios:

1. Half-duplex: Suitable for most scenarios (e.g., industrial sensors, access control systems), simple wiring (only 2 wires), low cost, but cannot send and receive simultaneously, requiring software coordination of communication timing (e.g., master-slave inquiry mode).
2. Full-duplex: Suitable for scenarios requiring simultaneous data transmission and reception (e.g., high-speed data transmission, real-time communication), high communication efficiency, but complex wiring (4 wires), higher cost, and less commonly used.

18. What are the transmission rates and interface definitions (VCC, D+, D-, GND) for USB buses (e.g., USB 2.0/3.0)?

• Transmission rates (common versions):

USB Version	Transmission Mode	Transmission Rate	Remarks
USB 1.1	Low-Speed	1.5Mbps	Early devices (e.g., mouse, keyboard)
USB 1.1	Full-Speed	12Mbps	Common peripherals (e.g., USB flash drives, printers)

USB 2.0	High-Speed	480Mbps	Mainstream version, compatible with 1.1
USB 3.0 (USB 3.1 Gen1)	SuperSpeed	5Gbps	Blue interface, backward compatible
USB 3.1 (USB 3.1 Gen2)	SuperSpeed+	10Gbps	Red interface, supports Type-C

• Interface definitions (taking Type-A interface as an example, 4 pins):

1. VCC (Pin 1): Positive power supply, outputs +5V voltage, maximum output current: USB 2.0 is 500mA, USB 3.0 is 900mA, used to power peripherals (e.g., USB flash drives, phone charging).
2. D- (Pin 2): Differential data line negative end, used with D+ to transmit data (differential signal has strong anti-interference).
3. D+ (Pin 3): Differential data line positive end, when low-speed devices (1.5Mbps), D- is pulled to ground, and when full-speed/high-speed devices, D+ is pulled to 3.3V, used to identify device types.
4. GND (Pin 4): Power ground, forms the power supply circuit, also serves as the signal reference ground.

• Supplement: USB 3.0 and above versions add 5 pins (total 9 pins) in the Type-A interface for super-speed data transmission, but are backward compatible with the 4 pins of USB 2.0, allowing compatibility with older devices.

19. What is the communication principle of Ethernet (e.g., RJ45 interface)? What are the advantages of its differential signal transmission method?

• Communication principle: Ethernet is a commonly used wired communication technology in local area networks, with the core being “frame transmission + CSMA/CD (Collision Detection)”:

1. Data encapsulation: The sender encapsulates data into an Ethernet frame (containing target MAC address, source MAC address, data length, data, and checksum) and sends it through the RJ45 interface to the network cable.
2. Transmission medium: Common twisted pairs (e.g., Cat5, Cat6), RJ45 interface has 8 pins, actually using 4 (pins 1, 2, 3, 6), divided into two pairs of differential lines (1-2 as one pair, 3-6 as another pair).
3. Collision detection (CSMA/CD): Before sending data, it first checks if the bus is idle; if idle, it sends; during sending, it checks for collisions (multiple devices sending simultaneously); if a collision occurs, it stops sending and waits a random time before retrying (suitable for half-duplex mode).
4. Receiving end: All devices receive the Ethernet frame, determining whether it is their frame through the target MAC address; if so, they receive and parse the data; otherwise, they discard it.

• Advantages of differential signal transmission (Ethernet uses differential signal transmission):
  1. Strong anti-interference capability: Differential signals transmit opposite polarity signals through two wires; external interference (e.g., electromagnetic interference) affects both wires simultaneously, and the receiving end can calculate the difference between the two wires to cancel out the interference, suitable for long-distance transmission.
  2. High transmission rate: The rising and falling edges of differential signals are steeper, supporting higher transmission rates (e.g., Cat6 twisted pairs support 10Gbps rates, with transmission distances up to 100 meters).
  3. Reduced power consumption: Compared to single-ended signals, differential signals have a smaller voltage swing (e.g., Ethernet differential signal swing is about 2V), reducing transmission power consumption.
  4. Long-distance transmission: Differential signals have low attenuation, and Cat5 twisted pairs support 100Mbps transmission over 100 meters, meeting local area network wiring needs.

20. What are the differences between SPI and I2C buses in terms of transmission rate, pin count, and multi-slave device support?

Comparison Dimension	SPI Bus	I2C Bus
Transmission Rate	High (up to tens of Mbps, e.g., 50Mbps), synchronous transmission, speed determined by SCLK	Medium (standard 100kbps, fast 400kbps, high-speed 1Mbps), synchronous transmission, speed limited by bus capacitance

Pin Count

Standard 4 (SCLK, MOSI, MISO, CS), additional CS lines needed for multiple slaves (or daisy chaining)

Only 2 (SDA, SCL), all slave devices share the bus, no extra pins needed

Multi-Slave Device Support	Supported, requires multiple CS lines (flexible, can individually select any slave device) or daisy chaining (saves pins, lower efficiency)	Supported, distinguished by 7-bit/10-bit addresses (up to 127/1024 devices), no extra pins needed, simple control
Communication Method	Full duplex (simultaneous send and receive)	Half duplex (can only send or receive at the same time)

Address Allocation	No unified address protocol, devices are selected through CS lines, no address configuration needed	Has a standard address protocol, slave devices need to be assigned unique addresses, which may lead to address conflicts
Anti-Interference Capability	Strong (differential clock synchronization, stable signals)	General (single-ended signals, requires good wiring and pull-up resistors)

Applicable Scenarios

High-speed data transmission (e.g., Flash, displays, ADC)

Medium-low speed, multi-slave devices, wiring constrained (e.g., sensor arrays, small modules)