SiFive is a global leader in RISC-V chip design, founded in 2015 by the inventors of the RISC-V architecture, and headquartered in California, USA. As a core driver of the RISC-V ecosystem, SiFive provides processor IP, toolchains, and customized chip solutions based on the RISC-V instruction set, covering a wide range of application scenarios from … Read more
In the field of embedded systems and real-time optimization, efficient linear algebra operations are a core bottleneck. Traditional BLAS libraries such as OpenBLAS or MKL, while powerful, often exhibit inefficiencies and poor cache utilization for small matrices (dimensions in the hundreds). Project Homepage The BLASFEO project stands out as an open-source library led by Gianluca … Read more
It is time to establish a high-performance “progress bar” for RISC-V. The Jiachen Project invites RISC-V vendors to donate machines to participate in the co-construction of PTS. Background, Mission, and Historical Significance of PTS The idea of the RISC-V Open Source Software Performance Tracking System (Performance Tracking System, PTS) was first conceived in 2020. At … Read more
It is time to establish a high-performance “progress bar” for RISC-V. The Jiachen Project invites RISC-V vendors to donate machines to participate in the co-construction of PTS. Background, Mission, and Historical Significance of PTS The idea of the RISC-V Open Source Software Performance Tracking System (Performance Tracking System, PTS) was first conceived in 2020. At … Read more
(Source: semiwiki)Data centers are typically seen as a battleground between CPUs (x86, ARM, RISC-V) and GPUs (NVIDIA, AMD, custom ASICs). However, behind this prominent competition, a quiet revolution is taking place: ARM is quietly replacing Intel and AMD in the data processing unit (DPU) market.The DPU (also known as SmartNIC) is responsible for the “pipeline” … Read more
【Article Summary】: The BOOM chip will be showcased at HotChips30-2018, demonstrating the complete process from CPU core source code to CPU chip tape-out, validating the idea that the best way to understand a chip is to create it. This creation process begins with chip programming. The article points out that under the RISC-V ecosystem, chip … Read more
Name: UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation Software: Quartus Language: Verilog Code Function: UART serial transmission and reception of strings Simulated transmission string “from my RISC-V SoC UART !!!!!!” 1. Project Files Edit 2. Program Files Edit 3. Testbench Edit 4. Simulation Diagram Edit Partial Code Display: `timescale 1ns / … Read more
NEWS TODAY Zhongke Benyuan has successfully developed the second generation of the RISC-V architecture 32-bit floating-point DSP core, SummerCore™, which is optimized for real-time control. Its performance reaches five times that of the TI C28x core and can be widely applied in industrial control, new energy, electric vehicles, and power electronics scenarios. SummerCore adopts the … Read more
1. Chip Origin: A Semiconductor IP Platform with Two Decades of Technological Accumulation 1.1. Establishment History and Technological Evolution • Founding and Positioning (2001-2010) Chip Origin was established in 2001, originating from the Shanghai branch of Celestry, a U.S. company, and is one of the first integrated circuit design companies in China. Initially focused on … Read more
The FDM320RV335 is a high-performance 32-bit floating-point DSP processor optimized for real-time control applications. This chip is based on Zhongke Benyuan’s self-developed RISC-V architecture DSP core, SpringCore1.0, with a working frequency of 150MHz. It integrates high-precision ADC, high-resolution PWM, eCAP, and eQEP interfaces on-chip, enabling high-performance motor control and power control. Application scenarios include industrial … Read more