1. Preface Learning with questions, some thoughts on exceptions/interrupts: (1) In a large system like the one below, when the CPU is running in OP-TEE OS, and suddenly an interrupt (like a Bluetooth interrupt) that needs to be handled by the Linux Kernel arrives, what is the software and hardware flow at this moment? (2) … Read more
Among them, el0_sync is the entry address for system synchronous exceptions; el0_irq is the entry address for interrupt exceptions; first, look at synchronous exceptions, where el0_svc is the exception caused by the system call svc;kernel_entry 0: indicates that this is a kernel jump from el0 to el1, performing register saving for user space, mainly saved … Read more
Click the blue "Arm Selected" in the upper left corner and choose "Set as Favorite" First, let’s look at a block diagram. After an interrupt occurs, the PC will jump to VBAR + interrupt offset. For example, the blue part in the diagram There are three base addresses: VBAR_EL1, VBAR_EL3, and VBAR_EL1 (secure). Which one … Read more
ver0.3 Introduction In previous articles, we introduced the ARM architecture’s interrupt controller GIC, which maintains a state machine for each interrupt signal. This interrupt state machine supports four states: Inactive, Pending, Active, and Active and Pending. The GIC maintains the status of each signal through internal registers and performs state transitions under relevant trigger conditions. … Read more
ver0.2 Introduction Previously, we introduced the core content of the General Interrupt Controller (GIC), an important component in the ARM architecture. Through a series of preceding articles, we elaborated on the system architecture of GIC, core components, interrupt types, interrupt signal routing mechanisms, state machine management, interrupt priorities, and other fundamental concepts. We believe that … Read more
Half-Watt’s ARM series articles: • ARM Documentation Series Part One: System Software Engineers View on ARM • ARM Documentation Series Part Two: ARM CPU Documentation • ARM Documentation Series Part Three: ARM CPU TRM – Taking Cortex-A76 as an Example • ARM Documentation Series Part Four: CoreSight Architecture and TRM • How to Play with … Read more
Click the blue "Arm Selected" in the top left corner and select "Set as Star" Environment: Linux kernel 4.4, (SCR.IRQ=0, SCR.FIQ=1) OP-TEE 3.6 (SCR.IRQ=0, SCR.FIQ=0) ARMV8GICV3 When the CPU is in the secure side and a non-secure interrupt arrives, depending on SCR.NS=0 / the interrupt in the non-secure group 1 group, the CPU interface will … Read more
Click the blue 'Arm Selection' at the top left and select 'Mark as Favorite' 1. Concepts of Exceptions and Interrupts AArch64 exception and interrupt handling In the AArch64 architecture, exceptions and interrupts are one of the key mechanisms to ensure the normal operation of the system. An exception refers to a situation where the system … Read more
To use the Cortex-M microcontroller in general applications, one needs to understand several aspects, including the programming model, how exceptions (such as interrupts) are handled, memory mapping, how to use peripherals, and how to utilize the software driver libraries provided by the microcontroller vendor. First, let’s take a look at the programming model of the … Read more
Course Reminder This live stream is a training course for the Amlogic Technology Cup of the Innovation Competition, mainly sharing the design and implementation of a music player based on Cortex-M0 on the FPGA chip from Anlu Technology. First, the course will review the basic principles of FPGA and its development process, introducing the resources … Read more