Source: Tiger Says Chip Original Author: Tiger Says Chip This article introduces chips specifically designed for AI computation. In the context of the rapid development of artificial intelligence (AI), traditional general-purpose processors (such as CPUs) can no longer meet the growing computational demands. Therefore, AI chips have emerged as the core hardware driving the popularization … Read more
Where Does the “Speed” of FPGAs Come From? Among processor families, FPGAs (Field Programmable Gate Arrays) are renowned for their “hardware-level acceleration,” particularly excelling in fields such as high-performance computing, image processing, and communication protocol processing. Their “speed” does not solely rely on clock frequency (many FPGAs operate at only a few hundred MHz, far … Read more
Click on the blue word to follow us In today’s digital age, artificial intelligence (AI) is everywhere, profoundly changing our way of life. From the intelligent voice assistant accurately identifying instructions on mobile phones, to the safe driving of self-driving cars in complex road conditions, to the keen capture of abnormal behavior by security monitoring … Read more
In the medical field, every technological innovation is crucial to health and hope. Today, we are witnessing a wave of upgrades in medical imaging devices led by FPGAs (Field-Programmable Gate Arrays), which act like a precise surgical knife, opening up a new path for hardware acceleration of image processing algorithms, making medical diagnosis more efficient … Read more
1. What is NPU? NPU (Neural Processing Unit) is a dedicated hardware accelerator specifically designed for neural network computations, with the primary goal of efficiently executing inference and training tasks for deep learning models. Unlike CPUs and GPUs, NPUs optimize matrix multiply-accumulate operations (MAC), activation functions, and quantization calculations through a customized architecture, significantly enhancing … Read more
Overview The Crypto Engine in the Linux kernel is an efficient encryption queue manager specifically designed to manage and schedule the execution of hardware cryptographic accelerators. Its primary goal is to efficiently offload cryptographic operations (such as encryption, decryption, hashing, authentication, etc.) to dedicated hardware, thereby significantly improving system performance and reducing CPU load. The … Read more
Recommended by Professor Bao Yungang: Sharing an innovative work jointly published by the Xiangshan team at the top architecture conference MICRO 2025: DiffTest-H (1) Origin DiffTest, originating from the field of software engineering, stands for Differential Test. Its core idea is that for two correct implementations based on a unified specification, given the same defined … Read more
Introduction: Recently, I have been working on data processing related to acceleration, needing to integrate acceleration into displacement. I found that there isn’t much information available online, so I will summarize what I have done recently! There are mainly two methods for integration: time-domain integration and frequency-domain integration. A common issue with integration is the … Read more
In today’s era, the benefits brought by Moore’s Law are slowing down, and the Multi-Die system provides a way to integrate multiple heterogeneous die (small chips) in a single package, reducing power consumption and improving performance for compute-intensive applications. For this reason, Multi-Die systems are rapidly becoming the preferred architecture for hyperscale users, autonomous vehicle … Read more
●●● On August 1, 2025, Ankai Micro officially launched the AK1037 series low-power lock control SoC chip designed specifically for smart locks. This series of chips integrates core functions such as fingerprint recognition acceleration, RFID card recognition, BLE, touch buttons, and voice broadcasting, achieving a high level of integration. A high-performance, ultra-low-power system platform and … Read more