Whether you are an IC design engineer, verification engineer, FPGA engineer, architecture engineer, or a student in microelectronics, you must be familiar with the ARM architecture. Choosing the Arm architecture is a very suitable option because its advantages include easy commercial promotion, the ability to utilize Arm’s mature ecosystem, and use Arm’s mature IP. Coupled … Read more
The official documentation (<span>ARM ARM</span>) introduction is as follows: Translating the English related to <span>MPIDR_EL1</span>, it is as follows: Function: Provides an additional PE (process element) identification mechanism for scheduling in multi-processor systems. Attributes: MPIDR_EL1 is a 64-bit register. Field values: [63:40]: Reserved, RES0. [39:32]: Affinity level 3. For more information, refer to the description … Read more
1. Preface Learning with questions, some thoughts on exceptions/interrupts: (1) In a large system like the one below, when the CPU is running in OP-TEE OS, and suddenly an interrupt (like a Bluetooth interrupt) that needs to be handled by the Linux Kernel arrives, what is the software and hardware flow at this moment? (2) … Read more
1 Stage 1 Page Table Attributes (Attribute fields in stage 1 VMSAv8-64 Block and Page descriptors) PBHA, bits[62:59]: for FEAT_HPDS2 XN or UXN, bit[54]: Execute-never or Unprivileged execute-never PXN, bit[53]: Privileged execute-never Contiguous, bit[52]: The translation table entry is contiguous and can exist in a TLB Entry DBM, bit[51]: Dirty Bit Modifier GP, bit[50]: for … Read more
Click the card below to follow Arm Technology Academy This article is organized by the WeChat public account Arm Selected, and mainly shares the related content of Armv8 Cache Coherency Solution: MOESI protocol. 1. MOESI State Definitions The Armv8 architecture uses the MOESI protocol to maintain data consistency between multiple cores. The MOESI protocol describes … Read more
1. Introduction The Cortex-M processor series is based on the M-Profile architecture, providing low latency and high determinism for deep embedded systems. Our latest generation Cortex-M processor is the Cortex-M55. The Cortex-M55 is the first processor based on the Armv8.1-M architecture, featuring vector processing extensions with Arm Helium technology. The Cortex-M55 brings higher levels of … Read more
Click the blue "Arm Selected" at the top left and select "Set as Star" 1. Background With the development of the times and the advancement of technology, the trend for security needs has become increasingly evident. ARM has been continuously adjusting and updating its new architectures, many of which are related to security. Below are … Read more
Background: Why There Is a Switch in Execution States In a large system, when we refer to it as 64-bit or 32-bit, we often mean the kernel. In fact, within such a large system, there are multiple layers of images, and not all of them are 64-bit or 32-bit. The following diagram illustrates a commonly … Read more
Introduction to Cache Cache is a block of memory in ARM that can be accessed at high speed. Each cache block contains: 1. Main memory address information; 2. Cached data. Cache can significantly increase the average speed of memory access. Cache has the following two characteristics: 1. Access locations are spatially limited. An access to … Read more
1. Pseudo-LRU and LRU Cache replacement strategies are used to determine which cache items should be replaced when the cache space is full. Pseudo-LRU (Pseudo-Least Recently Used) and LRU (Least Recently Used) are both common cache replacement strategies, and they have the following differences: Principle: LRU: The LRU strategy determines the usage frequency of cache … Read more