NAND Flash cannot achieve XIP, which is entirely determined by its underlying hardware implementation technology and interface standards, rather than something that can be easily changed by software or the operating system. This stands in stark contrast to NOR Flash, which supports XIP, with the core difference being the access interface and addressing method.Interface Bus:NOR Flash: has independent address and data buses. The CPU can directly provide any address through the address lines, just like accessing RAM, and immediately retrieve the data from that address via the data lines. This “memory-mapped” feature is a strict requirement for XIP.
NAND Flash: has only multiplexed I/O ports (usually 8 bits), with no independent address lines. It transmits commands first, then addresses, and finally data through the same set of pins. This process requires the Flash controller to issue a series of complex command sequences, making it impossible for the CPU to directly obtain instructions through a simple address.
Read Units and Internal Structure:
NOR Flash: can be read by byte or word.
NAND Flash: the basic unit of reading is a “page” (e.g., 4KB, 8KB, 16KB). To read a specific byte, the entire page of data must first be read into an SRAM buffer called “page cache,” from which the CPU can then read that specific byte. This process is very slow and results in significant latency (on the order of tens of microseconds). In contrast, the CPU executes instructions at the nanosecond level, making such latency unacceptable.
Bad Block Management and Wear Leveling:
NOR Flash: typically has no or very simple management.
NAND Flash: due to manufacturing issues, it comes with bad blocks from the factory and has a limited write lifespan. Therefore, it must be managed through a complex “Flash Translation Layer” (FTL). The FTL dynamically maps logical addresses to different physical blocks to achieve wear leveling and bad block masking.This means that a program’s logical code segment may be stored in physical block A today, but tomorrow it could be moved to physical block B by the FTL. The code’s position on the physical medium is not fixed! This fundamentally conflicts with the requirement of XIP that “code must be stored at a fixed, known physical address.”
Summary:
NAND Flash’s inability to achieve XIP is determined by its DNA:
-
“Serial Interface” prevents the CPU from directly addressing it, requiring complex command sequences.
-
“Page Read” mechanism leads to extremely high random read latency, failing to meet the real-time requirements of CPU instruction fetching.
-
“Dynamic Address Mapping” means that code does not have a fixed physical address, undermining the foundation of XIP.
These characteristics make NAND Flash an excellent, high-density, low-cost data storage medium, but an extremely poor code execution medium. Therefore, in general computing systems, we utilize the large capacity and low cost of NAND Flash to store programs and data, and then load them into RAM— a medium designed for code execution— at runtime, thus achieving the best balance of performance and cost.