The Memory Protection Unit (MPU) is a computer hardware unit that provides memory protection functionality, typically integrated within the CPU. The MPU is a simplified version of the Memory Management Unit (MMU), offering only memory protection support, often used in low-power processors that do not require features like virtual memory management.[1]
The MPU allows programs running in privileged mode to define memory ranges, allocate memory access permissions, and set attributes for each range. Different processors support different memory partitioning; the Cortex-M7 series can have 8 or 16 memory partitions, and for the S32G, it can support 16 memory partitions.
MPU of Cortex-M7
The storage interface of the Cortex-M7 based MCU is shown in the figure below[2]:
When configuring/operating the MPU, we set it based on regions; each region can have different access rules, and the storage type and their attributes determine the behavior of accessing this partition.
When partitioning, it is common to encounter overlapping partition addresses, in which case the partition attributes will be determined by the settings of the higher partition number. For instance, if the MPU can set 16 partitions, the attributes of partition number 15 will be the final attributes for that address range.
The Cortex-M7 has a unified MPU storage mapping table, meaning that execution access and data access have the same partition settings.
Besides the aforementioned 8 or 16 partitions of the Cortex-M7, there is also an optional background region, which has the same access attributes as the default storage mapping table but can only be accessed by software running in privileged mode.[3]
If a program attempts to access a region prohibited by the MPU, the processor will throw a MemManage fault (which can be caught as an exception). In an operating system environment, such behavior may ultimately lead to termination of execution. During OS execution, the kernel can dynamically update the MPU partition settings based on the tasks that need to run.
Types and Attributes
As mentioned, the type and attributes of a partition determine the access behavior.
There are two types: Normal and Device/Strongly-Ordered.
For Normal type partitions, the processor may reorder transactions for efficiency or perform speculative reads. In contrast, for Device/Strongly-Ordered type partitions, the processor must maintain the execution order of transactions according to code order.
Of course, the two subtypes of Device and Strongly-Ordered have different execution order requirements; external storage can cache data intended to be written to devices, but caching for data written to Strongly-Ordered storage is not allowed.
Additionally, there are two attributes: whether it is shareable (shareable) and whether execution is prohibited (execute never/XN).
When the Shareable attribute is set, the storage system will provide different data synchronization mechanisms for different bus masters, such as processors with DMA controllers.
Strongly-Ordered partitions must be Shareable.
If multiple bus masters can access a non-shareable area, software must ensure data consistency between different buses.
If the XN attribute is set, the processor will prevent instruction access to this area, otherwise it will throw an exception.
A more detailed introduction to attributes can be found in the RASR register (as shown above); we will focus on XN, AP, TEX, C(Cacheable), B, S(Shareable) for now.
The values of TEX, C, B, and S control the attributes of the corresponding storage space. For details on combination, refer to Arm Cortex-M7 Devices Generic User Guide r1p2.
For Cortex-M7 partitions, the settings are generally as follows:
Using MPU
The MPU registers need to be set and enabled before use, typically completed during the application initialization phase after system startup.
Configuration operations generally consist of three steps:
-
Select a partition
-
Set attributes for the selected partition
-
Repeat the above two operations for other partitions
-
Enable the MPU
If it is desired to throw a memory management fault exception when accessing a partition without permission, the SHCSR register must be set before enabling the MPU.
Partition Size
The size of the partition can only be a power of 2, with a minimum of 32B, and can be set to 64B, 128B, 1KB, 1MB, etc., with a maximum of 4GB.
References
-
^Memory protection unit https://handwiki.org/wiki/Memory_protection_unit#:~:text=A%20memory%20protection%20unit%20%28MPU%29%2C%20is%20a%20computer,of%20memory%20management%20unit%28MMU%29%20providing%20only%20memory%20protectionsupport
-
^How to Configure the Memory Protection Unit (MPU) Tech Brief https://ww1.microchip.com/downloads/en/DeviceDoc/90003179A.pdf
-
^Optional Memory Protection Unit https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/Optional-Memory-Protection-Unit?lang=en