Introduction
On July 2, Siemens announced that it had received formal notification from the U.S. government to lift the export restrictions on Chinese chip design software (EDA). Within a day, the three major giants in the EDA field, Synopsys, Cadence, and Siemens EDA, confirmed that the U.S. Department of Commerce’s Bureau of Industry and Security (BIS) had lifted the temporary export ban on the Chinese market.
This technology blockade, which began on May 23, was suddenly reversed after just 35 days. Behind the policy flip-flop lies the reality of the deeply intertwined global semiconductor supply chain, as well as the intense competition between national interests and corporate demands.
Text Editor｜ Song Yuhan
1
Key Tools in Chip Design
What is EDA?
What is EDA? EDA stands for Electronic Design Automation. It is essential software for designing large-scale integrated circuits. If we compare a chip to the “brain” of an electronic device, then EDA software is the key “tool” for creating this “brain”. EDA is used to complete the design processes of ultra-large-scale integrated circuit chips, including functional design, synthesis, verification, and physical design (including layout, routing, layout design rule checking, etc.), and is known as the “mother of chips”. EDA tools cover the entire process of integrated circuit design, with the design of a high-performance processor involving the following steps: specification formulation – architecture design – logic design – verification – synthesis – layout planning – logic mapping – physical design – layout routing – final verification – manufacturing – mass production. Except for specification formulation, manufacturing, and mass production, every other stage requires specialized EDA tools to complete operations.
■ There is a close and interdependent relationship between EDA and computing power
As a “massive consumer” of computing power, EDA faces challenges in designing modern complex chips (such as SoC, CPU, etc.) due to complex design rules and the massive demand for physical effect simulation verification. Its core tasks, such as logic synthesis, layout routing, and physical verification, are extremely computationally intensive, and the EDA process for designing advanced process node chips requires a large number of CPU core hours. At the same time, computing power is a “key enabler” for EDA development; continuous growth in computing power is necessary to cope with increasing design complexity, achieve more accurate model simulations, support advanced algorithms, and shorten design cycles. The elastic computing power provided by cloud computing platforms has also promoted the development of EDA as a service. Furthermore, EDA is also a “key tool” for releasing and optimizing computing power, used to design “computing power engines” and dedicated hardware accelerators, optimizing chip energy efficiency, and supporting advanced packaging design to build powerful computing systems. The demand for computing power and the development of EDA present a “spiral upward” cycle of interdependence; designing more powerful chips requires more computing power, and designing these chips requires more advanced EDA tools, while developing and running advanced EDA tools also requires significant computing power, which in turn necessitates designing more powerful chips, with both continuously driving each other.
Thus, it is evident that EDA is not only the “digital foundation” of chip design but also a strategic stronghold for the semiconductor industry to break through physical limits and achieve technological sovereignty. From manual drawing to AI-driven design, from single-chip design to heterogeneous integration, every iteration of EDA technology profoundly reshapes the boundaries of innovation in the electronics industry. With the improvement of the Chinese EDA ecosystem and the acceleration of global technological integration, this field will continue to provide core support for emerging technologies such as artificial intelligence, 5G, and the Internet of Things.
2
The Sudden Ban
Unexpected Supply Cut
On May 23, the U.S. Department of Commerce’s Bureau of Industry and Security (BIS) suddenly issued a letter requiring the three major EDA companies to suspend exports of chip design tools related to military use and advanced processes (below 10nm) to China. This decision covers ECCN 3D991 (design software) and 3E991 (verification software) categories, taking immediate effect without a grace period.
EDA is known as the “mother of chips” and is almost irreplaceable in advanced processes below 7nm. The global EDA market is dominated by Synopsys, Cadence, and Siemens, which hold 90% of the market share. Domestic EDA companies in China are still in the growth stage and are highly dependent on these three giants.
After the ban was implemented, Chinese chip design companies were unable to update or download certain EDA tools, significantly impacting high-end chip research and development. Chinese chip design companies were suddenly “choked off”, facing a crisis of supply cut for design tools.
The market reaction was immediate. On the day the ban was announced, the global EDA sector lost over $10 billion in market value in a single day. Synopsys fell by 12%, and Cadence dropped by 9.8%, marking the largest single-day decline since 2020.
3. Multiple Games
Interest Balancing Behind the Unblocking
The ban was lifted quickly after just one month, reflecting the complex interplay of multiple interests.
Corporate interests suffered significantly. The revenue share of the three major EDA giants in China for 2024 is substantial, with Synopsys reaching 16% and Cadence reaching 12%. The ban led to a sharp decline in their stock prices, with market values evaporating by over $10 billion. The CEO of Synopsys admitted during the earnings call that the “revenue expectations for the Chinese market have been adjusted downward”, forcing a policy reversal.
The exchange of bargaining chips in the U.S.-China trade game. The timing of this unblocking coincided with the U.S.-China “90-day buffer period negotiations”, interpreted as the U.S. side releasing a gesture of easing. The background of the ban was the intense competition between the U.S. and China in rare earth trade—China’s export controls on seven types of heavy rare earths in April directly impacted the U.S. military and new energy industries.
The capital market reacted positively to the unblocking. After the policy reversal, the EDA sector in the U.S. stock market rebounded by 3.5% in a single day, with Synopsys and Cadence’s stock prices rising by over 5% and 6%, respectively. This reflects investors’ recognition of the “limited unblocking” maintaining the commercial fundamentals.
The limitations of the unblocking and the risks that remain
Although the unblocking brings short-term benefits, the fundamental challenges facing the Chinese chip industry have not been eliminated.
The risk of technological dependence still exists. The global EDA market presents a highly monopolized pattern, with a scale reaching $15.71 billion in 2024, and the three major giants holding a combined market share of 74%. The domestic EDA market in China has a localization rate of less than 15%, and in the advanced process field below 5nm, it is even lower than 5%.
The possibility of policy flip-flops is high. The U.S. technology control over China exhibits a cycle of “testing-pressuring-partial adjustment”. The current unblocking only covers Siemens, while Synopsys and Cadence have not yet confirmed their unblocking. The U.S. Department of Commerce still retains restrictions on ethane exports.
Despite the rapid development of Chinese EDA companies in recent years, there is still a significant gap compared to international giants in terms of full-process coverage, advanced node support, and ecological collaboration. Against the backdrop of global market fluctuations and geopolitical tensions, the demand for China’s semiconductor industry is rising against the trend, while the industry’s deep dependence on foreign EDA vendors has become an unavoidable “Achilles’ heel” in the development of China’s digital economy. The restoration of supply from the three major EDA manufacturers has alleviated the immediate crisis, but this is by no means the end of the crisis. The Chinese semiconductor industry must accelerate breakthroughs in “root technologies” such as EDA and build an independent innovation ecosystem to truly break free from constraints and gain the initiative for long-term development. This incident may become a key turning point in the process of autonomy for China’s EDA and even the entire semiconductor industry.
Conclusion:
Historically, changes in the scale of technology control often resonate with fluctuations in geopolitical situations. In the current international environment, China’s chip industry must build a more resilient technological innovation ecosystem—leveraging strategic opportunities during technological windows to accelerate the accumulation of key capabilities; and firmly adhering to the core path of independent innovation, ensuring that the initiative in technological development is always in its own hands. The global technological game surrounding EDA tools profoundly reveals that in the context of increasing anti-globalization trends, core technological sovereignty is not a gift from the outside, but a strategic capability that must be forged through continuous efforts.
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