Recently, Tesla joined the RISC-V Foundation and is considering using free RISC-V designs in its new chips. So far, more than 100 technology companies, including IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google, and Huawei, have joined the RISC-V camp.
The reason for this phenomenon is partly due to the exorbitant licensing fees of ARM, and partly because RISC-V offers a completely open instruction set, which has great potential to become the Linux of the CPU field. Recognizing the future of RISC-V, many tech giants have invested early while RISC-V was still a potential stock.
The Birth of RISC-V
In 2010, a research team at the University of California, Berkeley, was preparing to launch a new project. To design a CPU, they had to choose an instruction set. However, the X86 instruction set is tightly controlled by Intel, and the ARM instruction set licensing fees are very high, while MIPS, SPARC, and PowerPC also have intellectual property issues.
In this situation, the Berkeley research team decided to design a completely new instruction set from scratch. This new instruction set had to meet the needs of processors of various sizes, from microcontrollers to supercomputers. As is often said in the industry, designing an instruction set is not black magic; implementing a CPU using that instruction set is the real valuable work. The Berkeley research team completed the development of the RISC-V instruction set in just three months and publicly released the first version of the instruction set.
The first version of the instruction set contained only less than 50 instructions, which could be used to implement a processor with basic functions such as fixed-point operations and privileged modes. Users could also customize new instructions based on their needs.
This made the instruction set both concise and flexible. Subsequently, the Berkeley research team named this new instruction set RISC-V, where RISC stands for Reduced Instruction Set Computing and V is the Roman numeral representing the fifth generation, as Professor David Patterson from Berkeley had already developed four generations of processor chips before this.
More importantly, the Berkeley research team made the RISC-V instruction set completely open, using the BSD License open-source agreement, which means that RISC-V does not require paid licensing like ARM or PowerPC. The BSD open-source agreement grants users significant freedom, allowing them to modify and redistribute the open-source code, and also allows the development of commercial software for release and sale based on the open-source code. Unlike the GPL agreement of Linux, which restricts commercial companies, the BSD open-source agreement is different; for example, Apple’s iOS is based on the BSD kernel, but after using open-source software, Apple can still keep iOS closed-source and profit in the commercial market due to the flexibility granted by the BSD open-source agreement.
For academic institutions such as universities and research institutes, RISC-V is also very valuable. A research team led by researcher Bao Yungang from the Institute of Computing Technology, Chinese Academy of Sciences, initially chose SUN’s Open Sparc T1 for a project, but this processor had poor community activity and software support, and its independence was lacking. They then chose Micro Blaze, but this processor was not open-source. Finally, they turned their attention to RISC-V and completed their research project. The related technological achievements were used by Huawei in HiSilicon’s ARM server CPU.
Because RISC-V chose a very commercial-friendly BSD open-source agreement, along with its advantages of being concise and flexible, many commercial companies have begun to pay attention to RISC-V.
RV12 RISC-V Processor
RISC-V is expected to replicate the success of Linux. Currently, in the CPU market, X86 and ARM are the two dominant players. However, both of these giants are very domineering; Intel does not allow any company other than AMD and VIA to use the X86 instruction set, and once AMD is acquired, the licensing for the X86 instruction set must be renegotiated. Even when Altera tried to sidestep this by translation, they were ultimately dragged down by Intel’s patent lawsuits.
Similarly, while ARM is somewhat better than Intel, it is only marginally so. The licensing for instruction sets is also very stingy; only a handful of companies have obtained ARM32 licenses, and while there are more ARM64 licenses, the licensing fees are exorbitant. The French chip startup Greenwave stated that if they used the ARM architecture, they would have to spend $15 million on licensing fees. Moreover, after the license expires, whether to continue licensing and the licensing fees must be renegotiated.
Because of the excessively stringent licensing of X86 and ARM, many large companies are very dissatisfied with Intel and ARM, which has given opportunities to up-and-coming players like RISC-V. Companies such as Google, Huawei, IBM, Micron, NVIDIA, Qualcomm, Samsung, Western Digital, as well as academic institutions like the University of California, Berkeley, MIT, Princeton University, ETH Zurich, Indian Institute of Technology, Lawrence Livermore National Laboratory, Nanyang Technological University in Singapore, and the Institute of Computing Technology, Chinese Academy of Sciences, have all joined RISC-V. At the 7th RISC-V Workshop held in November 2017, a total of 138 companies and 35 universities and research institutions participated globally.
In addition to commercial companies and academic institutions, the Indian government is particularly fond of RISC-V. In 2011, India began implementing a processor strategy plan, funding 2-3 projects nationwide to develop processors. Professors G. S. Madhusudan and V. Kamakoti from the Indian Institute of Technology Madras initiated the SHAKTI processor project under this plan, choosing RISC-V and receiving over $90 million in funding from the Indian government.
In 2016, the Advanced Computing Development Center in India received $45 million in funding from the Indian Ministry of Electronics and Information Technology, aiming to develop a 2GHz quad-core processor based on the RISC-V instruction set.
In recent years, processor-related projects funded by the Indian government have increasingly gravitated towards RISC-V, making RISC-V the de facto national instruction set of India.
Currently, the Berkeley research team has completed a sequential execution 64-bit processor core based on the RISC-V instruction set (codenamed Rocket), and has conducted 12 tape-outs based on 45nm and 28nm processes. The Rocket chip has a clock frequency greater than 1GHz, and its measured performance is 10% higher than that of the ARM Cortex-A5, with an area efficiency 49% higher, and dynamic power consumption per unit frequency is only 43% of that of the Cortex-A5. In the embedded field, Rocket is already competitive with ARM.
As a result, Western Digital announced that it will use 1 billion RISC-V cores annually; NVIDIA also announced that it will use RISC-V for internal controllers in GPUs. The US DARPA is funding some companies to design aerospace chips based on RISC-V; many commercial companies are planning to develop IoT smart chips, security chips, and motherboard management controllers for servers based on RISC-V. The software ecosystem is also gradually improving, with common developer tools such as debugging toolchains, interrupt controllers, JVM, LLVM, and Python being refined.
Thanks to being open-source and free, commercial companies and academic institutions worldwide can develop processors compatible with the RISC-V instruction set without paying a dime. This makes RISC-V likely to be widely adopted by global developers and replicate the miracle of Linux. Moreover, the BSD open-source agreement of RISC-V is more friendly to commercial companies than the GPL agreement, providing strong motivation for commercial companies to promote this initiative.
Conclusion
Indeed, relying on open-source and free access, RISC-V is very favored by universities and research institutes, and is expected to excel in the educational field, which will continuously cultivate a steady stream of talent for RISC-V. For commercial companies, due to the exorbitant licensing fees of ARM, there is also a strong motivation to pursue RISC-V as a backup, avoiding being tied down to ARM.
However, RISC-V also faces a concern: the lack of a strong leader, which may lead to fragmentation issues. In the past, MIPS was also very academic; commercial companies in the MIPS camp could freely add instructions, such as Loongson adding over 1000 new instructions based on MIPS, thus forming its own instruction set, LoongISA. This led to software development needing to differentiate between Loongson version and MIPS version, even though they both belonged to MIPS.
Since RISC-V also allows users to add new instructions, this could lead to fragmentation; perhaps in the future, RISC-V processors developed by Huawei, Qualcomm, and Google, while all belonging to RISC-V, may not be able to run the same software.
After all, complete openness and strong leadership are contradictory; if this issue cannot be resolved, it will be difficult for RISC-V to grow to a level where it can compete with X86 and ARM. Thanks to researcher Bao Yungang from the Institute of Computing Technology, Chinese Academy of Sciences, for guiding this article!
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