The “Nano-Level Polishing” of Chips: How CMP Smooths Multi-Layer Circuits?

In chip manufacturing, there is an “invisible hero”—without it, multi-layer metal circuits would resemble “uneven mountain roads,” making precise lithography impossible, and achieving 7nm or 5nm processes would be a fantasy. This hero isChemical Mechanical Polishing (CMP), which can control the surface undulations of silicon wafers within 50Å (0.005μm), achieving true “global flattening.” Today, we will start from the “undulation problem” of silicon wafers and dissect the working logic, key variables, and industry trends of CMP.

1. First, understand: Why must chips be “flat”? — The crisis of silicon wafer undulation

Chips are not “single-layer circuits” but rather multi-layer stacked structures (such as Metal1, ILD insulation layer, Metal2), similar to multi-layer circuit boards stacked together. If the surface has undulations:

• During lithography, the lens focal length cannot simultaneously align with high and low points, causing fine lines to be misaligned;

• During metal wiring, connections are easily broken at the steps, leading to chip short circuits or open circuits;

• After multiple layers are stacked, the undulations will “accumulate,” ultimately making it impossible to achieve precise circuits.

Early flattening technologies (such as thermal reflow and spin-coated glass) could only achieve “local flattening,” such as rounding step angles and filling small gaps, but could not eliminate the overall undulation of the entire silicon wafer. CMP is currently the only technology that can achieve “global flattening”—not only local flattening but also significantly reducing the step height across the entire surface of the silicon wafer, which is key for chips entering deep sub-micron processes (below 0.35μm).

2. The working principle of CMP: A “cyclical operation” of chemistry + mechanics

The core logic of CMP is particularly clever:First, apply a “peelable oxide film (chemical action)” to the surface of the silicon wafer, then grind away the oxide film and the surface protrusions together (mechanical action), repeating the cycle until flat..

The specific process is as follows:

1. Chemical etching: The oxidants in the polishing solution (such as H₂O₂) generate a soft oxide film on the surface of the silicon wafer (for example, silicon generates SiO₂, copper generates CuO);

1. Mechanical grinding: The nano abrasives in the polishing solution (such as SiO₂, Al₂O₃) grind away the oxide film while removing surface protrusions under the action of the polishing pad;

1. Repetition: The oxide film in the recessed areas is not ground away, and the corrosion inhibitor in the polishing solution will apply a “protective layer” to the recessed areas to prevent excessive corrosion; after the oxide film on the protruding areas is ground away, a new exposed surface will generate an oxide film and continue to be ground until the entire surface is flat.

For different materials, the details of CMP will be adjusted:

• Silicon / Oxide film CMP: Uses alkaline polishing solution (pH 10-11), SiO₂ abrasives, and relies on ammonia to etch the SiO₂ oxide film;

• Tungsten CMP: Uses acidic polishing solution (pH < 3), Al₂O₃ abrasives (hardness close to tungsten), and relies on the “oxidation-grinding” self-limiting process to remove tungsten;

• Copper CMP: Copper is soft and difficult to etch, using the “Damascus process”—first groove, fill with copper, then use CMP to grind away excess copper on the surface, with the polishing solution containing hydrogen peroxide + acetic acid, achieving rates of up to 1600nm/min.

3. The “three key variables” of CMP: A slight deviation can lead to “failure”

The effectiveness of CMP relies on the matching of “process parameters, polishing solution, and polishing pad”—even a slight deviation in one parameter can lead to scratches on the silicon wafer, over-polishing (removing too much), or uneven polishing.

1. Process parameters: Precise control is key

• Polishing speed: Too fast can cause excessive lubrication of the polishing solution, reducing the removal rate and possibly leading to “over-polishing” (breaking the circuit); too slow results in low productivity, generally controlled within the speed range suitable for the abrasives and polishing pad;

• Polishing pressure: Must be uniform! Uneven pressure can lead to faster polishing in some areas and slower in others, creating new undulations; typically adjusted based on abrasive hardness, for example, tungsten CMP pressure is slightly higher than silicon CMP;

• Polishing solution flow rate: Too little can lead to the accumulation of reactants, hindering abrasive circulation; too much is wasteful, generally aiming for “just enough to cover the polishing pad and timely remove waste”;

• Polishing time: Cannot be too long (over-polishing) or too short (not flat), needs to be calculated based on the removal rate, generally 1-3 minutes.

2. Polishing solution: The “ammunition” of CMP, composition determines effectiveness

The polishing solution is the “core consumable” of CMP, with its composition hiding great knowledge:

• Abrasives: Determine grinding efficiency and surface quality. For example, the mainstream Cabot polishing solution uses SiO₂ abrasives sintered at high temperatures (1800℃)—uniform particles and high purity reduce scratches, with a global market share exceeding 80%;

• Oxidants: Quickly generate soft oxide films, such as hydrogen peroxide for copper CMP and KIO₃ for tungsten CMP;

• Complexing agents: Combine with metal ions to prevent abrasives from scratching the surface;

• pH value: Silicon / oxide film CMP uses alkaline (pH 10-11, to keep SiO₂ abrasives dispersed), while metal CMP uses acidic (pH < 3, to prevent metal oxide films from dissolving too slowly);

• Surfactants: Adjust the viscosity of the polishing solution and can also act as corrosion inhibitors, protecting recessed areas from excessive corrosion.

3. Polishing pad: The “cloth” of CMP, choosing the right pad is half the battle

The polishing pad is not only a “grinding tool carrier” but also responsible for storing polishing solution and removing waste; choosing the wrong one will directly affect flatness:

• Polyurethane pads(such as Rodel IC1000): High hardness, low compressibility, can accurately grind away protrusions, good flatness, but can easily scratch the surface;

• Non-woven pads(such as Rodel Suba IV): Soft and elastic, can improve surface roughness, but poor flatness;

• Composite pads(IC1000+Suba IV): Balances flatness and uniformity, currently the mainstream choice for oxide film CMP;

• Maintenance key: Polishing pads will “glaze” (surface becomes flat, unable to store liquid) after prolonged use, modern equipment is equipped with “polishing pad conditioners” for real-time wear control, extending lifespan and stabilizing processes.

4. CMP equipment: From “slow work produces fine products” to “efficient mass production”

The development of CMP equipment has always focused on two cores: “precision” and “capacity”:

• Early equipment: Represented by IPEC Westech 372, could process fewer than 20 wafers per hour, excelling in precision but low in capacity;

• Mid-term improvements: SpeedFam, Cybeq, etc., introduced “multi-head single platforms” that can polish multiple wafers at once, significantly improving capacity;

• Future trends: As wafer sizes evolve from 300mm to 450mm, equipment will require more precise pressure control, temperature control (to avoid degradation of polishing solution), and automation for loading and unloading; “single-head/double-head precision control” is more suitable for larger wafers—after all, even slight pressure deviations on 450mm wafers can lead to uneven polishing at the edges and center.

5. The “duality” of CMP: Outstanding advantages, challenges remain

Advantages: Unmatched global flattening capability

1. Can achieve “global flattening,” controlling step height within 50Å, a necessity for 7nm/5nm processes;

1. Compatible with various materials (silicon, oxide film, tungsten, copper), even polishing multi-layer materials;

1. Can improve step coverage of metal wiring, reducing defects such as short circuits and open circuits;

1. Does not use hazardous gases, relatively safe.

Disadvantages: Narrow process window, high threshold

1. Many process variables (pressure, speed, polishing solution concentration), narrow window, slight deviations can cause issues;

1. Thickness and uniformity are difficult to control, requiring precise endpoint detection (such as real-time measurement of wafer thickness);

1. Equipment is expensive, with single machines costing millions, making it difficult for small and medium-sized manufacturers to afford;

1. Cleaning after polishing is difficult: Residual abrasives or metal particles can dry and form “track defects” (metal embedded scratches), requiring megasonic cleaning + dilute HF treatment.

Conclusion: CMP—The key to “flattening” chips and the “cornerstone” of process advancement

From 0.35μm to 3nm, the circuits of chips are becoming denser and the number of layers increasing, raising the requirements for CMP—such as controlling “depressions” (pits caused by excessive copper polishing) for copper CMP, and requiring higher local flatness for oxide film CMP.

CMP may seem like a “rough job” of “polishing,” but it is actually one of the most delicate processes in semiconductor manufacturing—it must “grind flat,” “not scratch,” and be “efficient.” In the future, as chips move towards smaller processes and larger wafers, breakthroughs in CMP technology will continue to be a significant driving force for the semiconductor industry.