Many of the chips in your daily devices like smartphones, routers, and cars are ASICs (Application-Specific Integrated Circuits) — custom chips designed for specific functions. But did you know? An ASIC chip goes through over 30 critical steps from the idea of ‘I want to make a chip that can process signals’ to receiving a working product in hand, involving design and production phases. Any mistake at any step could lead to significant losses (with a single tape-out costing millions). Today, let’s take a straightforward look at the ‘entire journey of ASIC chip birth’~
1. Understanding First: ASIC Design Development is ‘Blueprinting + Framework Building’
Design is the ‘soul’ of the chip, determining what the chip can do and its performance. The documentation breaks down the design process into five core stages, each step aimed at ‘risk mitigation’:
1. Preliminary Preparation: From ‘Requirements’ to ‘Blueprint Framework’
- Research Phase: First, clarify ‘what problem the chip needs to solve’, for example, ‘to create a chip that can process 4G signals’, and set performance indicators (such as clock frequency, power consumption);
- Top-Level Design + Module Division: Break down major functions into smaller modules, like dividing a house into a living room and bedroom — for instance, a signal processing chip can be divided into ‘receiving module, decoding module, storage module’;
- RTL Coding: Use hardware description languages (like Verilog) to write each module into code, akin to ‘drawing construction plans for each room’, and insert DFT (Design for Testability) to facilitate later problem identification.
2. Simulation Verification: ‘Let the Blueprint Run and Check for Bugs’
Once the design is complete, it cannot be directly produced; it must first undergo ‘virtual testing’, which is crucial to avoid tape-out failures:
- Dynamic Simulation: Run the RTL code with test data to check if the output is correct, for example, sending simulated signals to the receiving module to see if it can decode correctly, akin to ‘simulating chip operation on a computer’;
- Formal Verification: Use mathematical methods to compare ‘consistency before and after design’ — for example, checking if the RTL code and the synthesized gate-level netlist are the same, without running data, directly checking logical equivalence to avoid ‘introducing new problems while modifying code’;
- Static Timing Analysis (STA): Use PrimeTime tools to check ‘if signals can arrive on time’, for example, the time difference of clock signals reaching each module cannot be too large; otherwise, the chip will ‘respond slowly’, which is critical for deep submicron processes (like 0.18μm and below).
3. Synthesis: ‘Transforming Code into Circuit Diagrams’
- Using tools like Design Compiler, convert RTL code into a ‘gate-level netlist’ (which uses AND, OR logic gates to build the circuit), while considering the technology library (for example, standard cells for TSMC 0.18μm process), and insert scan chains (to facilitate later testing).
- This step is akin to ‘turning construction plans into a real materials list’, determining which ‘parts’ will be used to build the circuit.
4. Backend Layout: ‘Transforming Circuit Diagrams into Manufacturable Layouts’
The design cannot remain at the logical level; it must be transformed into physical graphics on the wafer:
- Layout and Routing: First, ‘place’ the logic gates on the wafer layout (layout), then connect them with wires (routing), and insert a clock tree (to ensure clock signals reach each module evenly);
- Physical Verification: Perform LVS (Layout vs. Schematic, checking if connections are correct) and DRC (Design Rule Check, checking if the layout meets manufacturing requirements, such as wire spacing); if this step fails, the factory cannot produce.
5. Test Preparation: ‘Preparing a Health Check List for the Chip’
- Generate test vectors (equivalent to ‘health check items’), such as CP test vectors (pre-packaging functional tests) and FT test vectors (final tests post-packaging), ensuring that the produced chips can be quickly tested for quality.
2. Next, Manufacturing: From ‘Silicon Ore’ to ‘Finished Chips’
Once the designed layout (GDSII file) is handed over to the foundry, it enters the ‘physical manufacturing’ phase, divided into front-end (wafer manufacturing) and back-end (packaging and testing), totaling 19 steps. We will highlight the key steps:
Front-End Processes: From ‘Silicon Rod’ to ‘Chips on Wafer’ (11 Core Steps)
The front-end is ‘transforming silicon ore into wafers with circuits’, like ‘engraving micro-circuits on silicon wafers’:
- Silicon Rod Stretching: Melt polycrystalline silicon in a quartz furnace and pull out high-purity single crystal silicon rods (equivalent to ‘creating a large single crystal silicon raw material’);
- Cutting and Polishing: Use diamond blades to cut the silicon rods into thin slices (the wafers), then polish them to a mirror finish (to ensure clarity for subsequent photolithography);
- Oxidation + Photolithography: Place the wafers in a furnace at 900-1100℃ for oxidation (forming a silicon oxide insulating layer on the surface), then coat with photoresist, using masks and exposure techniques to ‘draw circuit diagrams on the wafers’ (akin to ‘projecting circuit patterns onto the wafers’);
- Etching + Ion Implantation: Use chemical agents to remove the unprotected oxide layer (etching, to engrave patterns on the wafer), then implant ions like phosphorus and boron (to form the PN junction of transistors, equivalent to ‘adding switches to the circuit’);
- Forming Electrodes + Wafer Testing: Inject aluminum onto the wafer surface to form electrodes (to allow the chip to be powered), then conduct WAT (Wafer Acceptance Test) and CP (intermediate test, marking defective chips to avoid subsequent packaging waste).
Back-End Processes: From ‘Wafer Fragments’ to ‘Marketable Chips’ (8 Core Steps)
The back-end is ‘transforming bare chips on the wafer into usable finished products’, like ‘dressing bare chips in protective clothing + conducting health checks’:
- Cutting the Wafer: Use diamond blades to cut the wafer into individual bare chips (Die), discarding defective chips marked by CP;
- Mounting the Chip: Attach the good bare chips to a metal frame;
- Gold Wire Bonding: Use 25-micron pure gold wire (thinner than a hair) to connect the chip electrodes to the frame pins (to allow the chip to power external devices);
- Packaging: Encapsulate the chip in ceramic or resin (to protect against impact and oxidation; resin is commonly used for smartphone chips, while ceramic is often used for industrial chips);
- Burn-In Testing: Operate the chip under high temperature (e.g., 85℃) and high pressure (e.g., 1.2 times rated voltage) to preemptively eliminate ‘short-lived chips’ (to avoid users experiencing failures after a few days of use);
- Final Product Testing: Conduct FT (final testing, checking functionality and electrical characteristics), visual inspections, and mark qualified products with laser engravings (such as model number, production date), while discarding unqualified ones.
3. Key Reminders: These 3 Nodes are Most Likely to ‘Fall into Pits’
- Static Timing Analysis at the Design End: If not done well, the chip will have ‘timing issues’ — for example, signals may not arrive, leading to functional chaos, and the tape-out can only be scrapped;
- Photolithography Process at the Production End: Uneven photoresist coating or inaccurate exposure can lead to misaligned circuit patterns, rendering the entire wafer useless;
- Gold Wire Bonding at the Back-End: If the gold wire breaks or is not connected properly, the chip will have ‘poor contact’, which will only be discovered after packaging, wasting packaging costs.
Interactive Time
Which aspect of ASIC chip ‘design’ and ‘manufacturing’ do you think tests technology more? If you had to choose one aspect to delve deeper into, would you choose design or manufacturing? Let’s discuss in the comments~
#ASIC Chip Full Process #Chip Design Development #Semiconductor Manufacturing Process #Chip Production Steps #Application-Specific Integrated Circuits