Did you know? The high-end chips that can integrate billions of transistors rely entirely on EDA (Electronic Design Automation) technology to support them—without EDA tools, designers would take decades to manually draw layouts, while using EDA can complete the task in just a few days. This overview of integrated circuit EDA design explains the “past and present of EDA,” “design process,” and “future trends” clearly. Today, we will break it down in simple terms to help you understand how EDA helps us “quickly create chips.”~
1. First, let’s understand: What is EDA? The “super tool” for chip design.
EDA (Electronic Design Automation) can be simply described as “using computer software to assist in chip design,” providing full-process support from “idea” to “finished product.” Its core functions include three main aspects:
- Replacing manual work: No need to manually draw transistors and connections; the software automatically generates layouts, improving efficiency by over 100 times;
- Early verification: After design completion, simulation testing can be performed, such as “Will this circuit leak?” or “Is the speed fast enough?” to avoid discovering problems only after production;
- Adapting to processes: It can automatically adjust designs based on the foundry’s processes (e.g., TSMC 7nm, SMIC 14nm) without needing to redraw the layout.
EDA can handle a wide range of design types, from chips to circuit boards:
- Chip-level: IC layout design (e.g., CPU cores), PLD/FPGA design (programmable chips);
- Circuit-level: Analog chips (power management), digital chips (memory), mixed-signal chips (RF);
- Board-level: PCB design (mobile phone motherboard wiring).
2. How did EDA come about? Growing alongside electronic systems.
The development of EDA has completely synchronized with the complexity of electronic systems, driven by Moore’s Law:
- 1950-1970s: Electronic systems were still small-scale integrated circuits (SSI), with only a few to hundreds of transistors, relying on manual drawing and simple CAD tools, such as drawing a simple NAND gate;
- 1980s: Entering large-scale integrated circuits (LSI), with transistor counts exceeding ten thousand, CAE tools (Computer-Aided Engineering) began to be used for logic simulation and automatic layout and routing, such as the early design of the CPU 4004;
- 1990s to present: From very large scale integration (VLSI) to system-on-chip (SoC), transistor counts have grown from millions to billions, and EDA has upgraded to “high-level design,” using Verilog/VHDL languages to write designs that are automatically synthesized into circuits, such as today’s mobile phone SoC designs.
How powerful is today’s EDA? Taking Intel chips as an example: the 4004 (1971) had only a few thousand gates and used simple tools; the Core 2 (2006) has hundreds of millions of gates, all relying on EDA tools to complete the design cycle, which has been shortened from years to months.
3. The core: EDA design process, from “idea” to “chip” in 7 steps.
Whether designing an FPGA or ASIC, the EDA process follows a “top-down” logic, similar to “drawing blueprints before laying the foundation when building a house”:
1. Step one: Define requirements—What kind of chip do you want to make?
- Clarify functionality (e.g., “make a chip that can perform addition”), performance (speed must be 1GHz, low power consumption), and interfaces (must connect to memory);
- Use Matlab, C++, etc., for algorithm simulation to verify “can this function be realized,” such as simulating the logic of an adder on a computer first.
2. Step two: Write code—Describe the circuit using HDL.
- Use Verilog or VHDL (Hardware Description Language) to write code, which is not a software program but rather “hardware connection logic,” such as “how to connect the two inputs of the adder to the arithmetic unit”;
- For example: To create a 4-to-1 multiplexer, writing a few lines of code in Verilog can describe it, which is 10 times faster than hand-drawing the circuit diagram.
3. Step three: Functional simulation—”Run it on the computer first.”
- Use tools like ModelSim for simulation, adding “test stimuli” to the code (e.g., input 2 and 3 to the adder and check if the output is 5) to verify the logic is correct;
- This step does not consider actual hardware delays; it ensures that “the function is correct,” such as “will this circuit calculate incorrectly?”
4. Step four: Logic synthesis—Convert the code into a “gate-level netlist.”
- Use synthesis tools like Design Compiler to convert HDL code into “gate-level circuits” (using NAND gates, NOR gates, etc. to build circuits);
- It also needs to optimize based on the “process library” (parameters of gate circuits provided by the foundry), such as “how to layout to minimize area” and “how to connect to achieve the fastest speed.”
5. Step five: Layout and routing—”Find positions for the circuit and connect wires.”
- Layout: Place the synthesized gate circuits on the chip layout, such as “placing the adder on the left and the register on the right”;
- Routing: Use software to automatically connect wires, ensuring “all gate circuits are connected as designed,” while avoiding wire crossings and excessive delays (e.g., wires on critical paths cannot be too long);
- Tools: Use Quartus II for FPGA and Cadence Encounter for ASIC.
6. Step six: Timing simulation—Simulate “the speed of the real chip.”
- After layout and routing, there will be “delay data” (e.g., wire delays, gate delays), which are added to the simulation to see if “the speed is sufficient during actual operation”;
- For example, if designing a 1GHz chip, and the simulation finds that the critical path delay is 1.2ns (corresponding to a speed of 833MHz), then routing optimization is needed to shorten wire lengths.
7. Step seven: Download / tape-out—Transform into a “real chip.”
- If it is FPGA: Download the design files to the chip, such as programming a Xilinx FPGA with a download cable, and testing can be done immediately;
- If it is ASIC: Generate layout files (GDSII) and hand them over to the foundry for tape-out, such as TSMC making photomasks and producing wafers according to the layout.
4. The core capabilities of EDA: Synthesis and simulation, both are essential.
The two core functions of EDA tools determine the “correctness” and “performance” of the design:
1. Synthesis: Converting “high-level descriptions” into “low-level circuits.”
Synthesis is not a “simple translation” but “intelligent optimization.” For example, when converting Verilog code into a gate-level netlist, it performs two tasks:
- Transformation: Converts the description of the “adder” into a combination of “AND gates + OR gates + XOR gates”;
- Optimization: Selects the optimal solution based on constraints (minimum area, maximum speed, minimum power consumption), such as “using 3 gates to implement addition is more area-efficient than using 5 gates.”
It is entirely different from software compilers: software compilers only convert C language into CPU instructions and cannot change hardware structures; while EDA synthesizers can “create optimal circuit structures” based on process libraries, meaning the same code synthesized using 7nm technology and 14nm technology will yield completely different circuits.
2. Simulation: Discovering “all possible issues” in advance.
Simulation is divided into three categories, progressively verifying from “functionality” to “real environment”:
- Behavioral simulation: Checking “if the logic is correct,” such as “after pressing a button, will the output change as expected,” without considering delays;
- Functional simulation: Verifying the “logic of the gate-level circuit” after synthesis, such as “will the synthesized adder calculate incorrectly?”;
- Timing simulation: Validating “real working conditions” after adding delays, such as “will timing errors occur at high frequencies (Setup/Hold violations)?”
5. How to implement digital systems using EDA? 3 mainstream solutions.
Different needs require different implementation methods, and EDA tools will adjust the process accordingly:
1. FPGA: Quick verification, suitable for small batches.
FPGA is a “programmable chip”; you buy an off-the-shelf chip and use EDA tools to “write programs to implement functions,” such as prototype verification during the R&D phase:
- Advantages: No need for tape-out; samples can be produced in a few days, and design changes only require re-downloading, suitable for small batches (e.g., dozens to thousands of pieces);
- Process: HDL code → synthesis → layout and routing → download to FPGA, such as designing a simple controller using Quartus II;
- Common scenarios: New product development (e.g., 5G base station prototypes), teaching experiments.
2. ASIC: Mass production, suitable for large-scale.
ASIC is a “custom chip” designed specifically based on requirements, with low mass production costs, such as mobile phone SoCs and memory chips:
- Classification:
- Fully custom: Manually designing transistors and connections, pursuing ultimate performance (e.g., high-end CPU cores);
- Semi-custom: Automatically layout and route using standard cell libraries (off-the-shelf gate circuits), balancing cost and performance;
- Advantages: Small area, low power consumption, low cost (when mass production exceeds 100,000 pieces);
- Process: More steps than FPGA, including “layout verification” (DRC checks for wiring compliance) and “tape-out” steps.
3. SoC: Integrating a “complete system” on a single chip.
SoC (System on Chip) integrates the entire system onto a single chip, such as mobile phone SoCs that integrate CPU, GPU, memory, and RF. EDA must perform “hardware-software co-design”:
- Core: Quickly build using IP cores (pre-existing modules, such as ARM CPU cores, DDR memory interfaces) without starting from scratch;
- Role of EDA: Coordinate the timing and interfaces of different IP cores, such as “how the CPU and GPU transfer data via the bus,” and perform mixed-signal simulation (e.g., interference between power modules and digital cores).
6. Future trends of EDA: Moving towards “larger, faster, and more efficient.”
EDA will not stop at the present; it will upgrade in sync with chip technology, with four core trends:
- 1. High density + high speed: Supporting more advanced processes (3nm, 2nm), capable of designing chips with over 10 billion transistors, while also addressing the “line delay” issue (long wires slow down speed);
- 2. Low power + greening: As chip power consumption increases (e.g., CPUs generating significant heat), EDA will incorporate “power optimization,” such as “automatically turning off the power of idle modules;”
- 3. SOC/NOC integration: The communication bottleneck of SoCs is becoming increasingly apparent, and future designs will use NOC (Network on Chip), requiring EDA to support “router layout and data routing optimization,” such as enabling faster communication between multiple cores;
- 4. Dynamic reconfiguration: Chips can “change functions in real-time,” such as switching to “low-power mode” while on a call and “high-performance mode” while gaming, requiring EDA to support “partial reconfiguration design” without needing to re-download the entire design.
7. How widespread is the application of EDA? It’s everywhere in our lives.
Every electronic product you encounter daily has the shadow of EDA behind it:
- Digital products: mobile phone SoCs, computer CPUs, tablet GPUs;
- Smart devices: smart watch chips, smart home controllers;
- Industrial and medical: CNC machine chips, medical imaging device processors;
- Aerospace and automotive: in-vehicle chips (autonomous driving), aircraft navigation chips.
Interactive time
When did you first hear about EDA? If you could design a simple chip using EDA, what function would you want to design (e.g., “smart temperature control switch” or “simple calculator”)? Let’s discuss in the comments!~
#EDA Technology Introduction #Chip Design Process #FPGA Design #ASIC Development #SoC System Design #Electronic Design Automation