Recently, the Intelligent Software Center of the Institute of Software, Chinese Academy of Sciences, achieved significant progress in the field of computer systems, with their paperChimera: Transparent and High-Performance ISAX Heterogeneous Computing via Binary Rewriting being accepted at the top international conference in the field of computer systems, EuroSys 2026 (CCF-A category). This research innovatively proposes an efficient binary rewriting method aimed at the RISC-V instruction set, and based on this method, it introduces a new paradigm of ISAX heterogeneous computing for the RISC-V extended instruction set, achieving transparent and efficient migration of computing tasks between heterogeneous cores without modifying the source code, thus addressing the critical performance bottlenecks of traditional heterogeneous computing systems. The main authors of the paper include PhD student He Jiatai (first author), Assistant Researcher Qi Ji (corresponding author), Senior Engineer Yu Jiageng, and Researcher Wu Yanjun.
The ISAX (ISA+eXtension) heterogeneous computing architecture proposed in this study allows different cores (or processors) to share the same base instruction set while supporting different extended instruction sets. For example, some cores only support the base instruction set, while others additionally support vector instruction sets. This type of heterogeneity is quite common in the RISC-V architecture. For such scenarios, the ISAX system only needs to perform binary translation for a small number of extended instructions and write the results into the binary file, automatically switching between different versions of instructions at runtime based on the environment, thereby effectively reducing the overhead of heterogeneous scheduling and achieving transparency for users.
Existing methods have significant limitations in achieving the above goals: compilation methods rely on cumbersome configuration of compilation toolchains, consuming excessive resources and time; binary rewriting methods incur severe performance losses. On one hand, compilation methods require generating dedicated binary files adapted to specific hardware from source code through specific compilation toolchains based on hardware configurations. However, in edge scenarios, due to the high heterogeneity of device types, the resource and time costs consumed by the compilation process itself and toolchain configuration are unacceptable. In contrast, binary rewriting methods depend on existing binary analysis techniques to generate dedicated binary files through static analysis and instruction fragment modifications to support transparent scheduling. However, since binary analysis techniques cannot fully analyze and recover binary control flow, existing methods often adopt conservative strategies, ensuring that all possible control flows do not fail through inefficient rewriting methods or heavy runtime checks. Although this strategy guarantees correctness, it inevitably incurs significant runtime performance overhead.
To address this challenge, the team proposed an innovative solution based on co-design of hardware and software: as long as runtime errors are deterministic and recoverable, high performance of binary rewriting can be maintained while ensuring correctness. Specifically, the team utilized the encoding characteristics of the RISC-V instruction set to ensure that all unrecognized control flows trigger deterministic errors at runtime (such as segmentation faults or unrecognized instruction errors), and safely recover these errors through a lightweight runtime mechanism. With this mechanism, this research achieves efficient and transparent migration and scheduling between heterogeneous cores without the need for source code.
Overview of Chimera
To comprehensively evaluate the performance of Chimera, the team conducted comparative experiments with various state-of-the-art heterogeneous computing systems, including the natively compiled MELF (which relies on source code and is opaque to users), the binary rewriting-based Safer (which does not guarantee correctness), and the runtime scheduling-based FAM (Fault And Migration). The experimental results show that on hardware with inter-core instruction set heterogeneity, Chimera incurs only about 3.2% additional performance overhead compared to native compilation methods, while achieving an average performance improvement of about 12.5% and 33.1% over Safer and FAM, respectively. Furthermore, to further evaluate the performance of the rewritten binary files of Chimera, the team compared it with the SPEC CPU2017 benchmark and various state-of-the-art binary rewriting methods. The experimental results indicate that the method of Chimera achieves performance improvements of up to 42.5% compared to existing binary rewriting methods.
Performance Evaluation of Chimera Heterogeneous Computing
Performance Evaluation of Rewritten Binary Files of Chimera
In summary, this work proposes a new paradigm of heterogeneous computing based on RISC-V ISAX (ISA+eXtension), effectively resolving the hardware isolation and performance loss caused by semantic fragmentation in traditional heterogeneous computing systems, highlighting the unique advantages of the RISC-V architecture in heterogeneous computing. As the RISC-V architecture’s “Rosetta Stone”, this work achieves efficient execution of any RISC-V binary program on heterogeneous RISC-V processors without modifying the source code, seamlessly integrating with the existing software ecosystem, and providing pioneering exploration at the system software level to address the fragmentation challenges of RISC-V.
Source: Intelligent Software Research Center
