RISC-V’s 15th Anniversary: Strong Global Adoption Momentum

01

—

Rocky Linux Plans to Support RISC-V

Rocky Linux has officially announced plans to support RISC-V in the upcoming release of Rocky Linux 10, aligning with the Fedora RISC-V community.

Supported Platforms：

• ✅ StarFive VisionFive 2：Fully supported, ready to use with the standard RHEL10 kernel.

• ✅ QEMU：Provides full support, suitable for testing and evaluation.

• ⚠️ SiFive HiFive Premier P550：Limited support through vendor-provided kernel, some features may be restricted.

• ❌ Milk-V / Banana Pi：Currently not supported, may be considered in the future as upstream support matures.

  

Architecture Classification：RISC-V is classified as an “Alternative Architecture” (AltArch), meaning its build failures do not hinder the release process of other major architectures.

Build Method：Utilizes the toolchain from the Fedora RISC-V community and is maintained through the AltArch SIG, reflecting a “upstream first” collaborative model.

Related Topics：

As of May 2025, the support status of CentOS (RHEL derivative) for RISC-V architecture is as follows，covering several mainstream distributions: CentOS, AlmaLinux, Rocky Linux, Red Hat Enterprise Linux (RHEL)

Original link：https://linuxiac.com/rocky-linux-10-adds-official-risc-v-support/

02

—

15th Anniversary of RISC-V

RISC-V originated from the University of California, Berkeley, initiated by Professor Krste Asanović and his research team, with support from David Patterson, the father of RISC architecture, aiming to create a simple, modular, and extensible open instruction set to meet the needs of education and research.They believed that existing commercial ISAs were too complex to adapt to the new challenges following the slowdown of Moore’s Law and the end of Dennard scaling.Thus, RISC-V was designed as a “from the ground up” architecture, emphasizing openness and flexibility.

Although initially positioned for academic use, RISC-V quickly attracted industry attention.The first RISC-V workshop held in Monterey in 2015 was originally expected to be a small academic gathering but ended up attracting representatives from over 40 companies, marking the beginning of RISC-V’s commercialization.Its openness not only reduced costs but also significantly shortened the time from design to deployment, making it particularly attractive to startups. For example, NVIDIA decided in 2016 to replace its internal proprietary cores with RISC-V, marking a significant milestone for large semiconductor companies adopting RISC-V.

Professor Krste speaking at the 2025 RISC-V European Summit (Image source: RISC-V International Foundation)

Strategic Deployment in Europe and China

🇪🇺 Europe

Europe views RISC-V as a key tool for achieving technological sovereignty, reducing dependence on non-EU intellectual property.Europe accounts for about one-third of RISC-V International’s global membership and actively promotes applications in fields such as automotive and high-performance computing.For example, major automotive MCU suppliers like Infineon are planning to shift their future product lines to RISC-V architecture.

🇨🇳 China

China’s adoption of RISC-V is more strategic, aiming for technological self-sufficiency and reducing reliance on ISA controlled by the West.The government actively promotes RISC-V through policies and guidelines, leveraging its openness to bypass licensing fees and potential access restrictions.

Future Outlook

The open architecture of RISC-V is driving transformation in the global semiconductor industry, lowering entry barriers and fostering innovation.As more companies and countries adopt RISC-V, its ecosystem is expected to expand further, covering various fields from embedded devices to high-performance computing.The development of RISC-V demonstrates the tremendous potential of open hardware in driving technological advancement and achieving technological sovereignty.

Original link：https://www.eetimes.com/risc-v-turns-15-with-fast-global-adoption/

03

—

Technical University of Munich Develops New AI Chip

AI Pro is an innovative chip developed by the Technical University of Munich (TUM), which employs Hyperdimensional Computing methods to tightly integrate memory and computing units, mimicking the information processing of the human brain.

Innovative Features

• Efficient Learning：Unlike traditional deep learning models that require large amounts of data for training, AI Pro can perform pattern recognition with minimal semantic information. For example, it can recognize a car based solely on basic concepts like “a car has four wheels and drives on the road.”

• Energy Efficiency：This architecture significantly reduces reliance on large datasets, thereby lowering energy consumption, making it suitable for applications with high real-time and privacy requirements.

Chip Specifications

• Manufacturing Process：22nm process.

• Processor Architecture：Integrates a RISC-V processor with vector extensions.

• Computational Power：Supports dedicated fixed-point operations, combining VMAC-shift instructions to perform multiplication, accumulation, and shifting operations on multiple data points per clock cycle.

• Transistor Count：Approximately 10 million transistors, far fewer than NVIDIA’s 20 billion transistor AI chips.

Application Prospects

AI Pro is not intended to replace high-performance general-purpose AI chips but focuses on efficiently executing specific tasks on edge devices with extremely low energy consumption.

• Edge Computing：Suitable for scenarios requiring local AI inference, such as smart sensors and IoT devices.

• Privacy Protection：In fields with high data privacy requirements, such as healthcare and finance, AI Pro’s local processing capabilities help reduce data transmission and enhance privacy protection.

• Real-time Response：In applications requiring rapid response, such as autonomous driving and industrial control, AI Pro’s low-latency processing capabilities are advantageous.

Original link：https://www.hackster.io/news/ai-pro-chip-brings-on-device-intelligence-b429667368f2

04

—

Paper Review | A Confidential Computing Technology

IBM Research and the Max Planck Institute for Software Systems (MPI-SWS) have jointly released an open-source, royalty-free confidential computing technology called ACE (Assured Confidential Execution), specifically designed for embedded RISC-V systems.

Core Goals of ACE

ACE aims to enhance the security of embedded systems through the following means:

• Isolation of Sensitive Applications：Separating critical task applications from untrusted code to prevent data leakage.

• Formal Verification：Employing verifiable methodologies to ensure the correctness and security of system behavior.

• Open Source and Royalty-Free：Reducing deployment costs and promoting widespread application in industries such as healthcare, defense, and more.

Feasibility Assessment

Researchers deployed an ACE prototype on RISC-V hardware supporting virtualization and evaluated it, showing its practical feasibility in embedded environments.

Paper link: “ACE: Confidential Computing for Embedded RISC-V Systems”https://arxiv.org/abs/2505.12995

05

—

Armbian Adds Support for RISC-V Development Boards

Armbian 25.5 is the latest version released in May 2025, with the following new hardware support:

• TI SK-AM69（RISC-V Development Board）

• Banana Pi BPI-M2S

• Banana Pi M2+

• Orange Pi 3 LTS

• Orange Pi Zero2W

• TI SK-AM69：This is a high-performance RISC-V development board launched by Texas Instruments.

Configuration Tool Improvements

• Enhancements to armbian-config Tool：The new version of <span>armbian-config</span> supports modular application installation and system configuration, providing more flexible settings.

New Features

• Added Automated Build System Support for GitHub Actions；

• Provided more kernel configuration templates to simplify custom builds；

• Improved <span>build framework</span> stability.

Cleanup and Maintenance

• Fixed initial login issues for multiple boards；

• Removed outdated development board configurations that are no longer maintained.

Technical Details and Developer Improvements

• Better support for <span>extlinux.conf</span> boot format；

• Enhanced support for FDT (Flattened Device Tree)；

• Improved integration for custom U-Boot and Kernel.

RISC-V Related Highlights

• Armbian 25.5 adds official support for TI SK-AM69 RISC-V Development Board；

• Support for Banana Pi M2+ also contributes to the expansion of the RISC-V ecosystem.

Original link: https://www.phoronix.com/news/Armbian-25.5-Released

06

—

FPGA Device Capable of Playing Super Nintendo, GB, and PS Games

Sipeed Tang Mega is an FPGA-based development board designed for retro gaming enthusiasts and hardware developers.

Main Features

• FPGA Architecture：Utilizes GOWIN GW5AT series FPGA chips, providing high-performance hardware emulation capabilities.

• Rich Interfaces：Equipped with HDMI output, USB 3.0 interface, 40-pin GPIO, PMOD interface, etc., supporting various peripheral connections.

• Support for Multiple Game Cores：Supports NES, SNES, Game Boy, Game Boy Color, Game Boy Advance, Sega Mega Drive, Commodore Amiga, etc., with plans to support PlayStation, NeoGeo, and more in the future.

• Compact Design：Dimensions of only 65×56 mm, making it easy to integrate and carry.

• Pricing

• Tang Mega 60K：Starting at approximately $69.

• Tang Mega 138K：Starting at approximately $99

Technical Specifications

Model	LUT Count	Memory Configuration	Processor
Tang Mega 60K	60K	4GB DDR3, 468KB SSRAM, 2,124KB BSRAM	No hard-core processor
Tang Mega 138K	138K	8GB DDR3, 1,080KB SSRAM, 6,120KB BSRAM	Integrated 800MHz RISC-V AE350 processor

Original Link：

https://www.notebookcheck.net/Sipeed-Tang-Mega-This-FPGA-board-can-emulate-SNES-Nintendo-Game-Boy-and-PlayStation-games.1025517.0.html