(Source: riscv)The unstoppable rise of Artificial Intelligence (AI) across various industries is driven by multiple symbiotic factors. On a technical level, the explosion of usable data generated by digital and interconnected processes lays a solid foundation for AI training and inference. Meanwhile, advancements in processor and accelerator hardware, coupled with the proliferation of AI-ready software platforms and tools, provide the performance needed to handle data-intensive workloads. The flourishing of AI itself creates an environment that both private enterprises and government agencies are eager to participate in, thus stimulating an influx of investment that further accelerates growth.This growth is not just about more data and more computation; it is also about the trade-offs between cost, speed, and sustainability. The 2025 AI Infrastructure Summit emphasizes the importance of full-stack optimization of inference speed, enhancing energy efficiency at all levels, and balancing innovation with sustainability. These are fundamental elements for the successful future development of AI.The unprecedented development of AI has similarly impacted the demand for computing solutions that support AI implementation. According to Omdia, the global AI processor market is expected to reach $261.4 billion by 2025, with a projected compound annual growth rate (CAGR) of 8.1%, growing to $385.4 billion by 2030.
Crucially, while hardware accounts for about 70% of total market revenue, the software segment is growing rapidly, highlighting the strategic importance of deploying ready-to-use stacks and robust ecosystems.Modern AI encompasses a wide range of workloads, from battery-powered sensor algorithms and edge intelligent vision to data center-scale inference and space autonomous systems. Many of these workloads, especially the training of large-scale AI models, are pushing traditional architectures to their limits.Traditional closed architectures may excel in general-purpose computing, but their fixed instruction set architecture (ISA) and licensing models limit any deep customization for specific workloads. Although general-purpose processors have matured, they often lack the capabilities needed to optimize for inference latency, energy efficiency, real-time processing, or model specialization. Achieving these capabilities often requires the addition of neural processing units (NPUs) and other similar parallel computing hardware for modification.Today, as AI infrastructure spending skyrockets to $400 billion annually, the demand for AI-native hardware designed for full-stack optimization and energy efficiency at all levels is becoming increasingly urgent. By “AI-native,” we refer to customizable, efficient, and scalable systems designed from the ground up to make AI a foundational component (rather than an afterthought).RISC-V: The AI-Native Instruction Set Architecture (ISA)The debate over custom computing versus general computing is a key theme at the 2025 AI Infrastructure Summit, and RISC-V’s position is unequivocal. As an open and highly flexible ecosystem, RISC-V offers both standardization and customization, providing hardware developers with the freedom to build highly targeted AI-native chips. This is what makes RISC-V, which is just 15 years old and serves as an ISA, the preferred architecture for the next trillion-dollar AI investment.“The pace of AI development is faster than any other field, and RISC-V is the only architecture that can keep up,” said Dr. Philipp Tomsich, founder and CTO of VRULL GmbH and vice-chair of the RISC-V Technical Steering Committee. “RISC-V has the advantages of open standards, domain-specific acceleration, and liberation from traditional constraints, making it the foundation for AI-native innovation from edge devices to supercomputers.”To support this at the infrastructure level, hardware and software vendors need to collaborate to deploy AI-supporting hardware and supporting software across the entire stack. This encompasses everything from sensor-level microcontrollers (MCUs) to edge AI processors and high-performance cloud solutions in data centers.RISC-V has grown in the era of vectorization, scalability, and heterogeneous computing, with its level of custom instructions and domain-specific acceleration far exceeding what existing vendors’ proprietary cores can offer, providing a fit for future paradigms such as optical/photonics paths, composable infrastructure, and memory innovations.The “V” in RISC-V is always a subtle homage to vectors—reflecting founder Krste Asanović’s paper from the early 1990s on a vector machine for running neural networks. This includes extensions for scalable vector processing (with flexible vector lengths, which older SIMD models lack), mixed-precision data processing, and other accelerators built into the ISA rather than retrofitted.This architectural philosophy makes RISC-V a natural choice for AI-native, domain-specific computing—from ultra-low-power edge inference to data center transformer workloads—and it is not just theoretical. Mainstream hyperscale computing vendors, startups, and chip design companies have already proven its viability in customized, domain-specific AI chips.RISC-V also avoids the supply chain and roadmap development challenges that come with being locked into a single vendor. Access to the latest technologies is not always guaranteed, and obtaining a license for a proprietary ISA often means relinquishing some autonomy in roadmap development. In contrast, RISC-V empowers developers to innovate in their own way. It ensures that their chip strategies remain autonomous both technically and commercially.A New Open Approach is Needed for AI WorkloadsThe first phase of AI focused on shortening time-to-market for products. This led to platforms that are costly, space-consuming, and power-hungry. As a result, the cost of training models has now exceeded the affordability of the vast majority of customers.The RISC-V community sees us entering a new maturity phase driven by two major market forces:The need to create solutions for the edge, as challenges related to cost, power, performance, and area (PPA) become increasingly evident.The need to reduce the total cost of ownership (TCO) of cloud platforms.The RISC-V ISA is designed for modularity. Its dual advantages of standardization and customization make it an ideal choice for domain-specific computing, such as:Neural Processing Units (NPUs): NPUs are specialized processors optimized for running neural network computations. With RISC-V’s modular ISA, designers can tightly integrate NPUs to accelerate inference speed, reduce power consumption, and enhance real-time AI responsiveness across various industries, from mobile devices to automotive. They are excellent examples of full-stack inference speed optimization—one of the key themes of this year’s AI Infrastructure Summit.Tensor Acceleration Engines: Tensor accelerators handle large matrix multiplications, which are core to AI training and inference. RISC-V supports custom tensor extensions, allowing vendors to optimize throughput for specific workloads (such as recommendation engines, speech recognition, or large language models), which is crucial for efficient scaling.Compute-in-Memory (CiM): CiM architectures process data directly at the data storage location, reducing the costly movement between memory and processors. RISC-V’s scalability allows for seamless integration of CiM methods, which are vital for edge AI and IoT devices constrained by power and latency requirements.Optical or Neuromorphic Paths: Optical and neuromorphic computing paths simulate the brain or utilize light to transmit and process information with extreme efficiency. RISC-V provides the flexibility to connect these non-traditional paradigms with mainstream computing, paving the way for groundbreaking architectures for the next generation of AI workloads.In terms of AI workloads, transformer workloads (including large language models (LLMs) like GenAI and ChatGPT) represent the most significant breakthroughs today. These models also support visual and multimodal systems, heavily relying on matrix multiplications and attention mechanisms. With RISC-V, designers can add custom extensions and accelerators optimized for transformer workloads, making large-scale models easier to deploy across platforms and enhancing full-stack optimization to accelerate inference speed.Use cases for transformers include foundational model training, large-scale inference and serving, multimodal models that fuse vision and language, processing long-context transformers with millions of tokens, and specialized scientific and enterprise applications such as drug discovery, climate modeling, and protein folding.These LLM-driven workloads reflect the challenges emphasized at the AI Infra Summit—LLM performance bottlenecks, the sustainability of agent AI, and the demand for composable memory infrastructure.Hardware and Open Software Co-DesignModern chip development requires a co-design mindset: hardware functionality and software support must evolve in sync. RISC-V’s open model makes this possible, allowing hardware architects and software engineers to collaborate in real-time. New instructions and accelerators come equipped with ready-to-use toolchains, compilers, and libraries, enabling developers to start using them from day one. This tight feedback loop ensures that AI-centric scaling does not come from thin air but reflects actual workload demands and achieves end-to-end optimization.This focus also reflects the summit’s theme of “AI Building AI”: design automation and generative models accelerate the chip and software co-design cycle. This aligns perfectly with RISC-V’s broader philosophy: dynamic open-source infrastructure frameworks make the evolution of ISAs practically feasible. They enable vendors to quickly deploy the latest RISC-V variants without disrupting legacy software, ultimately enriching the software ecosystem while empowering chip innovation.This philosophy is reflected in the ongoing work defining AI-related instruction set extensions. Industry leaders from Akeana, Alibaba, Andes Technology, IBM, OpenChip, Rivos, Semidynamics, SiFive, Tenstorrent, Ventana, and VRULL are collaborating openly to establish standards that serve the global AI ecosystem. Task groups developing integrated matrix extensions (IME), matrix-vector extensions (VME), and additional matrix extensions (AME) are advancing the capabilities of efficient matrix operations—the cornerstone of modern AI workloads like transformers and deep learning.These efforts aim to achieve efficient matrix operations by tightly coupling hardware enhancements with corresponding software readiness, which is foundational for modern AI workloads like deep learning. Every design choice is data-driven. During the RISC-V standardization process, engineers analyze real machine learning (ML) and high-performance computing (HPC) workloads, identify software bottlenecks that hardware can address, and use prototype instructions to simulate “hypothetical” scenarios. These matrix solutions clearly demonstrate how software requirements and empirical data from actual workloads directly guide hardware design decisions.Specification drafts must use rigorous quantitative and qualitative arguments to clearly articulate the principles behind each instruction. The co-design of software and hardware ensures that both complement each other, avoiding the “chicken or egg” trap that isolated development often falls into. The rationale for extensions needs to be validated through rigorous performance analysis and measurements, ensuring that every new feature of the ISA addresses meaningful problems. RISC-V extensions adhere to evidence-based design and early software prototyping, thus avoiding “feature creep” and focusing on the most important functionalities for developers and end-users.Crucially, all of this is done in an open environment. Compiler, simulator, and library support are uploaded to LLVM, GCC, and the Linux kernel well before the chip is officially released. When the chip is officially taped out, the software stack (including machine learning frameworks like PyTorch and TensorFlow) has already fully leveraged its AI capabilities. This “zero-day” launch means that new hardware can immediately enhance performance in real applications and provide enterprises with the deployability guarantees that MLOps, confidential computing, and secure AI promise.Once again, standardization plays a critical role. RISC-V “profiles” bundle extension capabilities into guaranteed feature sets that software developers can confidently use. This confidence is further reinforced by providing standardized benchmarks across the ecosystem, guiding enterprises in their “build or buy” decisions. With the RVA23 platform expected to be approved by the end of 2024, hardware is anticipated to be available by 2026, providing both hardware vendors and software developers with a trusted platform standard. Canonical, Red Hat, and NVIDIA have already committed to providing support, indicating their confidence that their contributions will continue to thrive within the broad RISC-V ecosystem.This hardware-software co-engineering has yielded tangible results. Software upgrades have enabled a “zero-day” launch of the new RISC-V AI core—meaning that from the moment the silicon returns from the fab, the Linux operating system, compilers, and runtime libraries are already supporting its AI capabilities. The result is that hardware enhancements can be immediately translated into real performance improvements for AI applications, with no delays.Meanwhile, the nature of RISC-V allows companies to freely implement their instruction sets; although there are strict processes for how to do this. For power or performance, companies need to write libraries that directly map to their custom hardware while maintaining consistency at the application software layer. Today, every vendor is responsible for ensuring that software supports these customizations. A good example is the AI software stack, where standards like PyTorch or TensorFlow exist. Companies can decide to implement instruction sets that allow their software and hardware combinations to achieve significant advantages in metrics like power consumption or performance. The application software remains consistent, but companies need to write libraries that can fully leverage their custom hardware.In summary, RISC-V’s open co-design approach represents a scalable path to building AI-native platforms. From day one, the upstream software ecosystem supports every hardware enhancement. The synergy between toolchains, ISA innovations, and flexibility to meet current and future real AI demands is RISC-V’s powerful differentiating advantage. This enables RISC-V to rapidly deliver domain-specific innovations at the speed required in the AI era.RISC-V in the Real World: Tangible MomentumRISC-V has empowered AI-native chips designed to tackle modern AI challenges. The following companies are leveraging RISC-V to push boundaries:1. Andes Technology is one of the founding members of the RISC-V International Alliance, offering a comprehensive series of RISC-V IP cores with DSP, vector, and scalable capabilities, supported by automation tools for custom instruction extensions, enabling AI support in SoCs for applications ranging from ultra-low-power sensor nodes to data centers.2. Codasip provides customizable RISC-V cores for SoC developers using its CodAL design language. The company claims to have shipped over 2 billion cores, including configurations tailored for AI/ML edge use cases.3. NVIDIA offers a wealth of accelerator technologies that fuel AI’s growth. In 2024, RISC-V core shipments are expected to exceed 1 billion, while announcing plans to port its CUDA AI acceleration stack to the RVA23 architecture. This highlights that RISC-V’s significance has transcended the open software ecosystem, extending into mainstream AI applications, becoming a coordinator for the world’s leading proprietary GPU architectures.4. Semidynamics, a pioneer of integrated matrix extensions (IME) and IP core supplier in Europe, recently launched a RISC-V tensor unit (Tensor Unit) that supports streaming workloads, sparse/dense tensor computations, and AI data flow processing. By embedding vector and tensor capabilities into CPUs, Semidynamics is addressing core efficiency and PPA challenges in the AI data center space highlighted at the 2025 Infrastructure Summit.5. SiFive is a commercial vendor formed by the inventors of RISC-V, providing CPU cores suitable for AI use cases—from minimally configured edge sensors to enterprise-grade cloud infrastructure systems.6. SpacemiT is developing RISC-V processors for AI CPUs—its Muse Book and Deep Computing laptops are equipped with the K1 chip. The upcoming 64-core VitalStone V100 processor adopts the forthcoming RVA23 standard, designed to handle server-grade AI workloads.7. Tenstorrent builds high-performance AI processors using RISC-V CPU cores and chiplet architecture, focusing on scalable computing from edge to data center. The company is collaborating with Japan’s LSTC to develop a 2nm AI accelerator and has opened its chiplet specifications (OCA), thus building a composable and interoperable chip ecosystem.8. Ventana offers high-performance RISC-V processors and chipsets designed for scalable data center, AI, and automotive workloads. Its Veyron series achieves industry-leading single-thread performance and enables modular system integration through open chip standards like OCP Open Chiplet Economics (OCE). Ventana accelerates the adoption of RISC-V across all high-performance markets by combining its leadership and flexibility in computing.9. VRULL is committed to advancing the foundational research of the software stack, including runtime systems, toolchain optimization, and pre-tapeout exploration, to ensure RISC-V can evolve into a truly AI-capable platform. VRULL focuses on contributions to additional matrix extensions (AME) and IME based on real workloads and performance modeling to achieve outer product operations and other matrix patterns critical for AI inference.10. Xuantie, a brand under Alibaba’s Damo Academy, is dedicated to promoting RISC-V’s development in the cloud-to-edge AI space, designing server-grade processors like the Xuantie C930 aimed at AI-HPC applications. Xuantie is also driving compiler and toolchain support and contributing to new matrix extension standards, empowering autonomous domestic infrastructure.On the software side, the recently launched developer preview of Red Hat Enterprise Linux 10, in collaboration with the RISE project, was released on SiFive’s HiFive Premier P550, providing a mature enterprise-grade platform for building and deploying RISC-V-based AI workloads. Similarly, Canonical is preparing to offer Ubuntu desktop support for the RVA23 profile in the upcoming 25.10/26.04 releases, ensuring RISC-V developers have a stable, modern Linux distribution. The RVA23 will see more such milestone software moments—especially with RISC-V’s CUDA.Open projects like llama.cpp are now fully leveraging the 128-bit RISC-V vector extensions to accelerate quantization inference. With the support of the RISE program, the compiler team is providing upstream support for RISC-V in key AI frameworks like PyTorch, enhancing compatibility and performance without proprietary extensions.What does this mean for AI developers?For AI developers, RISC-V transforms the hardware landscape from proprietary constraints to an open platform that adapts to workloads rather than the other way around. This shift enables rapid innovation, supports workload specialization, and liberates from vendor lock-in.To shape and innovate the future of AI infrastructure, developers must seize the opportunities presented by RISC-V. Here’s how:Explore and Apply: Explore the growing ecosystem of RISC-V IP cores, development boards, and toolchains, and their role in full-stack inference optimization. Integrate RISC-V into your next-generation AI systems (whether at the edge or in the cloud) and experience the practical applications of AI-native hardware.Contribute and Collaborate: Join the RISC-V International organization—the standard-setting body behind the open ISA. Individual memberships are free, allowing participation in working groups; corporate members can join at various levels, from regular to premium, with associated fees and governance benefits. If you are a software developer, consider joining the RISE AI/ML working group—a community-led initiative under the Linux Foundation that helps drive the maturity of RISC-V’s AI software. This working group is dedicated to fostering collaboration among frameworks like PyTorch, TensorFlow, TFLite, and llama.cpp to ensure they perform optimally on RISC-V and directly impact LLM performance and agent AI readiness.Innovate and Optimize: Leverage RISC-V’s open modular ISA to co-design custom hardware and software. Tailor extension capabilities (such as vector, tensor, or matrix operations) to achieve unprecedented improvements in energy efficiency and latency at every layer, without sacrificing portability.Enhance Software Success: Developers who accelerate value realization by using RISC-V as their everyday development platform will achieve success. Gaining access to operational hardware is crucial, but working on RISC-V-equipped laptops is equally important. In fact, you can now purchase a DeepComputing RISC-V motherboard for the Framework Laptop 13, transforming the modular laptop into a fully functional RISC-V workstation, allowing you to build by running RISC-V on RISC-V. This real environment can enhance early adopters’ confidence, speed up porting, and deepen toolchain-level proficiency. Of course, if you prefer to start small, even a $5 Raspberry Pi Pico 2 comes equipped with RISC-V hardware for you to experiment with—we look forward to the launch of new RVA23-compatible development boards in 2026.In short, RISC-V disrupts the traditional model: hardware can now adapt to the realities of modern AI software. For those building the next generation of models, frameworks, and platforms, this means faster iteration speeds, shorter time-to-value (and thus lower costs), and a direct path from innovation to impact.