20220723: Issue 4
Kernel Updates
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v4: Fix RISC-V’s arch-topology reporting
The arm64 topology code is largely applicable to RISC-V as well, so it has been made generic along with the removal of MPIDR related code, which appears to be redundant since ‘3102bc0e6ac7 (“arm64: topology: Stop using MPIDR for topology information”)’ replaced the code that actually interacted with MPIDR with default values.
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v1: Support for RISCV64 architecture and common commands
This series of patches enables the crash tool to support the RISCV64 architecture and common commands (*, bt, p, rd, mod, log, set, struct, task, dis, etc.). To ensure the crash tool functions correctly for the RISCV64 architecture, a Linux kernel patch (currently under review) is required, which exports the kernel virtual memory layout, va_bits, and phys_ram_base to vmcoreinfo, simplifying the development of the crash tool.
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v1: Improve CLOCK_EVT_FEAT_C3STOP feature setting
This series enhances the RISC-V timer driver to set the CLOCK_EVT_FEAT_C3STOP feature based on RISC-V platform capabilities.
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v1: Fixes to work with the crash tool
This patch series consolidates these patches, along with a new patch 5. These five patches are fixes for kexec, vmcore, and improvements for vmcoreinfo and memory layout dump. With these five patches (patch 3 is essential), the crash tool can effectively analyze a vmcore.
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v5: Canaan device tree fixes
This series aims to eliminate dtbs_check errors for the RISC-V Canaan k210 based boards. To facilitate this, I modified the Canaan device tree Makefile to build all device trees in the directory if SOC_CANAAN is defined.
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v7: RISC-V IPI Improvements
These patches were originally part of the “Linux RISC-V ACLINT Support” series but are now a separate series to allow independent merging from the “Linux RISC-V ACLINT Support” series.
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V3: Support for 64-bit hartid on RV64 platforms
The hartid can be a 64-bit value on RV64 platforms. This series updates the code to support 64-bit hartid on RV64 platforms.
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v4: riscv: uprobe fix SR_SPIE set/clear handling
In RISC-V, the uprobe process clears spie before executing the original instruction and sets spie afterward. However, when accessing the page where the original instruction is placed, a page fault may occur, and interrupts are disabled in the arch_uprobe_pre_xol function, causing a WARN as follows.
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v1: Add HiFive Unmatched LEDs
This series adds support for the two LEDs on the HiFive Unmatched RISC-V board.
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v7: Add Sstc extension support
This series implements support for the Sstc extension, which was recently ratified. Prior to the Sstc extension, an SBI call was necessary to generate timer interrupts since only M-mode has access to the timecompare registers. This resulted in significant latency in generating timer interrupts at the kernel level.
Related Technology Updates
Qemu
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v6: target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to directly update the stimecmp CSR to program the next timer interrupt. This CSR is part of the recently ratified Sstc extension.
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v1: Fix pointer masking functionality for RISC-V
This patch corrects a typo that led to broken pointer masking functionality for RISC-V.
Buildroot
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v4: Fix RV64 NOMMU and add Canaan K210 SoC support
This series adds support for building 64-bit RISC-V NOMMU kernels (both bootable kernels and u-boot SD card boot environments) for NOMMU RISC-V 64-bit boards. Supported boards include QEMU and many boards using the dual-core RISC-V 64-bit Canaan Kendryte K210 SoC.