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Abstract:This paper studies the design of a lightweight physical layer protocol for space-based access networks and completes its application in the Feiteng edge computing node. A ground simulation system was established to implement the design of a technical verification scheme, providing a feasible technical approach for the research of physical layer access protocols for space-based edge computing nodes.
Keywords:Edge Computing, Space-Based Access Network, Physical Layer Protocol
This paper proposes a technical approach for the implementation of lightweight physical layer protocol software for space-based access networks, ensuring predictable and guaranteed network communication services for upper-layer communication applications.
01Introduction to Space-Based Edge Computing Node Hardware Platform
The hardware platform for space-based edge computing nodes adopts a scalable and modular design concept, utilizing 6U VPX standard modules for interconnection to achieve overall functionality. It mainly includes a Feiteng computing module, AI computing module, storage module, and power supply module, with each module communicating through a high-reliability, high-speed interconnect backplane.
The Feiteng computing module is designed with a domestic high-performance D2000 multi-core processor + co-processor FPGA + management FPGA architecture, as shown in Figure 1, forming a heterogeneous computing power combination that achieves high data throughput, high-performance data processing, high reliability, and strong scalability. The AI computing module is designed with an embedded neural network processor NPU + deep learning-based GPU + ARM MCU management architecture, forming a heterogeneous intelligent computing combination that realizes AI intelligent acceleration and deep computing for the space-based edge intelligent computing platform. The storage module is implemented with an FPGA + Flash architecture, providing efficient data storage and retrieval, achieving large capacity, high reliability, open, and poolable storage functionality. The power supply module adopts a modular design concept, containing power filtering, DC-DC conversion, and other functional circuits to achieve health management, remote communication, and protection functions against over-voltage and overheating, ensuring stable power supply to various functional modules of the whole machine. The high-reliability high-speed interconnect backplane uses a star network topology architecture, providing four slots for edge computing modules, AI computing modules, storage modules, and power supply modules, enabling high-speed, high-reliability interaction of heterogeneous computing unit data.
Figure 1 Feiteng Edge Computing Module
The chassis of the whole machine is designed according to the VITA78 standard, providing electrical interconnection and structural support for various functional boards, with multiple functional slots built-in, offering high scalability. It supports various bus interconnections including high-speed and low-speed, and adopts a cable-free design internally, reducing interconnection complexity while minimizing various signal conversion instances, optimizing electrical performance. The chassis is made of aluminum alloy 2A12 and employs a combination of forced air cooling and conduction cooling for heat dissipation, further optimizing the internal layout based on thermal simulation analysis to ensure environmental adaptability for space operations.
02Design of Lightweight Access Network Physical Layer Protocol Software
2.1 Waveform Verification Principle of Access Network Physical Layer Protocol
Software Defined Radio (SDR) is a technology that utilizes a general hardware platform to implement various communication modules through software. SDR technology is a software-based wireless communication technology that uses software to realize various functions in wireless communication systems, including signal processing, modulation and demodulation, encoding and decoding, and spectrum analysis. SDR systems are divided into three categories: FPGA-based SDR systems, DSP-based SDR systems, and GPP-based SDR systems. Among them, GPP-based SDR systems have a lower development threshold, lower development costs, shorter development cycles, and easier debugging compared to the other two types. GPP-based SDR systems are currently the most common implementation form of SDR systems. GPP-based SDR systems typically consist of two parts: GPP and peripherals. In this implementation process, a USRP peripheral was used. The principle of the SDR system is as follows:
2.1.1 Transmitter Principle
The principle of the SDR transmitter is shown in Figure 2, with the left side representing the host connected to the USRP peripheral, which can be a desktop or laptop computer, and the right side representing the USRP peripheral.
Figure 2 SDR Transmitter Principle Diagram
The SDR program is implemented using software communication modules, and various advanced programming languages can be used to write different communication modules on the host, such as Turbo coding modules, OFDM modules, etc. Given the high real-time requirements of SDR systems, C or C++ languages are generally used to write SDR programs. The SDR program contains the complete protocol stack of the communication system; for instance, if it is an LTE system, it includes PHY, MAC, RLC, PDCP, RRC, NAS, and even MME, etc.; if it is a WiFi system, it includes PHY, MAC, LLC, etc. The main function of the SDR program is to process the baseband data of the system.
UHD is the driver module for USRP devices, and different peripherals use different drivers. In this paper, the USRP device is used as the peripheral, so the driver module used is UHD. GPP also includes various system libraries and system call interfaces, as well as the kernel, to execute the SDR program. GPP transmits data to the USRP peripheral via USB 3.0. The USRP peripheral implements the transmission control module and digital upconversion module through FPGA design, enabling fast processing speeds. The transmission control module is used to control the sending behavior of the entire USRP, such as sending time, etc. The digital upconversion module is used to upconvert the baseband data generated by the host to an intermediate frequency. Afterward, the digital signal is converted to analog data by the DAC of the USRP, and after digital-to-analog conversion, it needs to undergo a low-pass filter to make the signal smoother. The intermediate frequency analog data is then multiplied by the signal generated by the crystal oscillator to modulate the intermediate frequency signal to the specified RF frequency point. Finally, the RF signal is transmitted out through a power amplifier.
2.1.2 Receiver Principle
The principle of the SDR receiver is shown in Figure 3, with the left side representing the host connected to the USRP peripheral, which can be a desktop or laptop computer, and the right side representing the USRP peripheral.
Figure 3 SDR Receiver Principle Diagram
First, the USRP device amplifies the received signal through a low-noise amplifier. Then, the signal after amplification is multiplied by the signal generated by the USRP crystal oscillator to downconvert the signal to an intermediate frequency, and similarly, it passes through a low-pass filter to smooth the signal. Afterward, the intermediate frequency signal is converted from the analog domain to the data domain through an ADC. The ADC is an important component in the USRP. The ADC is mainly controlled by two parameters: sampling precision and sampling rate. Sampling precision indicates how many bits are used to represent the sampled signal. For example, the ADC precision of the USRP B200 is 12 bits, meaning each sampled data point is represented by 12 bits. The sampling rate refers to the system’s sampling rate, for example, the sampling rate of the USRP B200 device is 61.44 MS/s. After the signal passes through the ADC, the digital signal is sent to the FPGA module for processing. The FPGA contains two modules: digital downconversion and reception control. The reception control is used to control the entire USRP system’s reception process, such as reception time, etc. The digital downconversion is used to downconvert the signal from intermediate frequency to baseband signal. Finally, after the digital signal is transmitted to the GPP device via USB 3.0, the GPP device processes the data with the SDR program to obtain the corresponding data.
2.2 Software Architecture Design and Implementation
The physical layer protocol software for space-based access networks consists of two sub-modules: signal transmission module and signal reception and display module. The software implements the physical layer protocol for space-based access networks using the “USRP+srsRAN” architecture, achieving signal transmission and reception functionality, including one eNB end, two UE ends, and three USRP nodes. Specifically, the signal transmission sub-module runs on the eNB node to send signals; the signal reception and display sub-module runs on the UE node to receive, parse, and display the results of the signals.
2.2.1 Signal Transmission Module
This module is responsible for encoding, multiplexing, modulating, spreading, scrambling, and framing the transmitted data to generate baseband signals; then, it converts the signal to intermediate frequency through digital upconversion and digital-to-analog conversion; finally, the intermediate frequency signal is sent out through the Ethernet physical interface after filtering, efficient power amplification, and upconversion processing.
2.2.2 Signal Reception and Display Module
This module is responsible for downconverting the signals received from the Ethernet physical interface, using low-noise power amplifiers and filtering to convert them into intermediate frequency signals; then, it generates baseband signals through analog-to-digital conversion and digital downconversion; finally, it synchronizes, estimates and equalizes the channel, despreads, demodulates, demultiplexes, and decodes the baseband signal to restore the original data and verify its correctness.
Three servers running the Galaxy Kirin operating system are set up for UE and eNB, with the UE’s IP addresses set to 192.168.250.128 and 192.168.250.133, and the eNB’s IP address set to 192.168.137.178. The software configuration deployment is shown in Figure 4.
Figure 4 Specific Implementation Architecture of the Software
In the design and implementation of the signal transmission sub-module on the Feiteng edge computing platform, it mainly completes power management, UHD deployment, RAN deployment, USRP test connection, and reliable operation of EPC and eNB; the signal reception and display sub-module mainly completes power management, UHD deployment, RAN deployment, USRP test connection, and reliable operation of UE. UHD provides functionality for interaction with USRP devices, ensuring normal communication between the host system and USRP devices. srsRAN is used to build and manage software-defined radio networks, completing the management of signal transmission and reception. The signal reception srsGUI provides graphical user interface functionality, supporting physical waveform verification. It is particularly important to note that during the srsRAN compilation process, the options –enable-float and –enable-sse must be used to allow single precision to avoid errors during compilation.
03Conclusion
Practical results show that the lightweight physical layer protocol software for space-based access networks proposed in this paper possesses high-quality information transmission and reception capabilities, meeting the communication service requirements of both high and low orbit satellites, providing predictable and guaranteed network communication services for upper layers, and also providing reliable underlying communication service guarantees for collaborative scheduling of resources and tasks in high-dynamic, time-varying topological environments.
References
1 Wu Wei. Overview of Integrated Information Network Development [J]. Integrated Information Network, 2020, 1(01): 1-16.
2 Sun Chenhua, Zhang Yasheng, Wang Linan, et al. Adaptability Analysis of 5G Ground Mobile Communication Technology in Low Orbit Constellations [J]. Radio Engineering, 2018, 48(03): 167-172.
3 Zhang Gengxin, Ding Xiaojin, Qu Zhicheng. Research on Integrated Internet of Things Architecture and Interference Analysis [J]. Integrated Information Network, 2020, 1(02): 22-33.
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