In semiconductor factories, the cleaning process has a set of “extremely strict” standards: since 2013, the number of metal atoms on the surface of each square centimeter of a wafer cannot exceed 0.5×10¹⁰ (equivalent to allowing only 5 soccer balls on a soccer field), the diameter of particles on the back must be less than 0.14μm (600 times thinner than a human hair), and the reduction of the oxide layer cannot exceed 0.4nm (equivalent to the diameter of just 2 silicon atoms). Once exceeded, an entire batch of chips may be scrapped. Today, we will break down the “full-process control” of semiconductor cleaning: from 4 types of deadly contaminants, to 5 mainstream cleaning methods, and to 3 major quality inspection techniques, we will see how chips transform from “dirty” to “ultra-clean”.
1. First, understand: 4 types of contaminants are the “deadly killers” of chips, and their sources are all around us.
The sensitivity of semiconductors to contamination is far beyond imagination—circuits at the 3nm process cannot tolerate particles larger than 0.05μm, nor can they withstand 10ppm of metal residue. The main contaminants are divided into 4 categories, each with clear sources and hazards:
1. Particles: the most “common” assassins, with sources from equipment and air.
- Source: debris from equipment wear, photoresist residues, floating dust in cleanroom air, and even tiny impurities in deionized water;
- Hazard: They adhere to the wafer surface through van der Waals forces, blocking photolithography light, leading to incomplete etching, and directly causing oxide layer breakdown, resulting in a sharp decline in yield;
- Key removal: Do not scrape hard (which can scratch the wafer), but rely on “chemical undercutting”—slightly etching the wafer surface to reduce particle adhesion, then rinsing them away.
2. Organic residues: barriers like “plastic wrap”, must be removed first to clean effectively.
- Source: operator skin oils, mechanical lubricants, photoresist residues, and even organic vapors in the cleanroom;
- Hazard: They form a transparent film on the wafer surface, preventing subsequent cleaning solutions from penetrating, effectively giving metals and particles a “protective coat”;
- Processing priority: Must be removed first! Commonly used sulfuric acid + hydrogen peroxide (SPM) carbonizes organic matter, then oxidizes it into CO₂ to blow away.
3. Metal contaminants: the culprits of “messy wiring”, with humans being the largest source.
- Source: ion implantation equipment, pipeline wear, chemical reagent impurities, and even operator gloves (which can carry Na and K ions);
- Common “culprits” and hazards:
- Precious metals (Au): exchange charge with hydrogen atoms on the silicon surface, adhering like “glue”, cannot be washed away with ordinary water, leading to leakage in the PN junction;
- Aluminum, iron: can penetrate the oxide layer during oxidation, affecting gate quality and causing threshold voltage shifts in MOS transistors;
- Attachment methods: There are two types—one directly bonds with silicon (difficult to remove), and the other hides in the oxide layer (removing the oxide layer can take it away).
4. Excess oxide layer: the trouble of “automatic rusting”, which forms in just 1 second.
- Formation speed: When a silicon wafer is exposed to air/water for 1 second, a natural oxide layer will form on the surface; the hydrogen peroxide used during cleaning can also promote the formation of a chemical oxide layer;
- Hazard: It hinders the conductive contact between metals and silicon, and can wrap around metal impurities, allowing impurities to penetrate into silicon at high temperatures, forming leakage paths;
- Exceptions: Useful oxide layers (such as gate oxide layers) must be “selectively retained”, only removing the excess parts.
2. How to clean? 5 mainstream cleaning methods, from “basic” to “advanced”.
In response to different contaminants and process requirements, the industry has explored 5 cleaning methods, each with its “specialized field”, like different “cleanliness packages” prepared for wafers:
1. RCA cleaning: a 50-year classic “basic model”, relying on two solutions to dominate.
This is the “industry standard” invented by RCA in the USA in 1970, centered around the chemical combination of “SC-1+SC-2”, suitable for mature processes (90nm and above):
- SC-1 (alkaline, NH₄OH+H₂O₂+H₂O=1:1:5~7): At 75-85℃, it slightly oxidizes the wafer surface with hydrogen peroxide, allowing particles to “detach” while also removing light organic matter;
- SC-2 (acidic, HCl+H₂O₂+H₂O=1:1:6~8): At the same temperature, hydrochloric acid forms soluble complexes with metal ions (e.g., Cu→CuCl₂), thoroughly removing metal contamination;
- Key step: After each cleaning step, it is essential to rinse with 18.2MΩ ultra-pure water (UPW) to avoid reagent residues—just like rinsing off shower gel after a bath.
2. Diluted RCA: the “cost-effective and environmentally friendly version”, reducing chemical usage by 80%.
Traditional RCA uses a large amount of strong acids and bases, which are expensive and dangerous; the improved “diluted version” addresses this issue:
- Core improvement: The water in SC-1 is increased from 5 parts to 50 parts, and SC-2 removes hydrogen peroxide, reducing chemical consumption by 80% and making operations safer;
- Effect remains unchanged: Even after dilution, it can still remove particles and metals, just taking slightly longer, suitable for cost-sensitive small and medium wafer fabs.
3. IMEC cleaning: the “advanced environmentally friendly version”, further reducing metal residues by 80%.
Developed by the Belgian research center IMEC, it relies on a combination of ozone and dilute acid, making it more environmentally friendly and cleaner than RCA:
- Three-step process:
① Ozone water removes organic matter: no sulfuric acid is used, reducing waste liquid, and extending the acid bath’s lifespan by 3 times;
② Dilute HF+HCl removes the oxide layer + prevents metal deposition: optimized ratios can suppress copper and silver ion deposition (copper deposition speed increases under light, and increasing Cl⁻ can form soluble complexes);
③ Ozone + HCl makes the surface hydrophilic: prevents water marks from drying, and adding nitric acid can reduce calcium contamination;
- Data speaks: After cleaning, copper residue decreased from 0.4×10³ atoms/cm² in improved RCA to < 0.07×10³ atoms/cm², with an 80% increase in metal removal rate.
4. Single-wafer cleaning: the “advanced process version”, eliminating cross-contamination.
As processes move to 45nm and below, traditional “batch cleaning” (washing 25 wafers together) easily leads to cross-contamination, making single-wafer cleaning a new choice:
- Core advantage: One wafer is cleaned at a time, avoiding contamination transfer between wafers, and allowing process adjustments based on each wafer’s contamination status;
- Applicable scenarios: Copper wires, low-k materials, and other fragile structures—these materials are sensitive to strong acids and mechanical friction from batch cleaning, and single-wafer cleaning can precisely control etching amounts to avoid damage.
5. Dry cleaning: the “waste-free version”, relying on plasma to “vaporize contaminants”.
Using no chemical solutions, it relies on gas reactions to remove contaminants, suitable for “water-sensitive” scenarios (such as after metal deposition):
- Mainstream technology: plasma cleaning:
① Place the wafer in a vacuum chamber and introduce gases like oxygen;
② Apply high-frequency voltage to turn the gas into “plasma” (with active particles);
③ Particles react with contaminants to generate gases like CO₂ and SiF₄, which are then pumped away by a vacuum pump;
- Advantages: No waste liquid, can perform localized cleaning; disadvantages: cannot completely remove metals (some metals have poor volatility at low temperatures), often used in conjunction with wet methods.
3. Cleaning equipment: ultrasonic cleaners are the “main force”, with dedicated processes for different wafers.
Good methods require good equipment to implement; in semiconductor cleaning equipment, ultrasonic cleaners are the “main players”, with other equipment matched as needed:
1. Ultrasonic cleaners: rely on “sound waves to dislodge particles”.
- Principle: 20-40kHz sound waves create “tiny shock waves” in the cleaning solution, dislodging particles hidden on the wafer surface, achieving 10 times the efficiency of manual cleaning;
- Dedicated processes: Different wafers have different cleaning steps, for example:
- Cutting wafers: ultrasonic rough cleaning → fine cleaning → pure water spray → rinsing (6 steps);
- Grinding wafers: hot pure water cleaning → hot alkaline water to remove grease → hot acid to remove metals → multi-step rinsing (8 steps);
- Epitaxial wafers: alternating cleaning agents + pure water cleaning → multi-step rinsing (9 steps).
2. Other auxiliary equipment: each has its “special skills”.
- Brush cleaners: Soft brushes combined with ultra-pure water remove large particles (below 2μm) left after CMP;
- Rotating sprayers: The wafer spins at high speed (3000r/min), spraying cleaning solution + ultra-pure water, using centrifugal force to fling away dirty water, and can clean and dry simultaneously;
- Overflow cleaners: Ultra-pure water flows in from the bottom of the tank and overflows from the top, continuously carrying away contaminants; traditional but reliable, though it consumes a lot of water.
4. How well is it cleaned? 3 major quality inspection methods “ensure” that no defects flow into the next process.
Cleaning is not the end; it must pass through 3 strict “physical examinations” to ensure the wafer meets the “cleanliness” standards:
1. Visual inspection: check if the surface is clean.
- Parallel beam inspection: Use parallel light to illuminate the wafer surface; if there are impurities, shadows will appear, allowing for intuitive judgment of surface cleanliness;
- 400x dark field microscope inspection: In a dark field, particles will reflect light, allowing precise detection of particles larger than 0.1μm.
2. Data inspection: check if the cleaning is thorough.
- Water resistivity inspection: Monitor the resistivity of the ultra-pure water from the last cleaning; if it reaches 18.2MΩ, it indicates no chemical residues (residues would lower resistivity);
- MOS high-frequency C-V testing: Create a temporary MOS structure to measure the capacitance-voltage curve; if the curve is abnormal, it indicates metal ion residues (which can cause threshold voltage shifts).
3. Indirect verification: check if subsequent processes meet standards.
- CVD silicon dioxide film detection: Deposit a layer of silicon dioxide on the cleaned wafer; if the film’s uniformity is poor or breakdown voltage is low, it indicates incomplete cleaning (contamination would affect film quality).
Conclusion: The “involution” of cleaning processes follows the process.
As chip processes advance from 7nm to 3nm, the “cleanliness” standards of cleaning processes are also upgrading—the limit on metal atoms may drop to 0.1×10¹⁰ atoms/cm², particle diameters must be less than 0.1μm, and oxide layer reductions must be controlled within 0.2nm. This means that cleaning is no longer an “auxiliary process” but a “key link” determining the yield of advanced processes.
After all, no matter how powerful the chip design is, it must first be “cleaned” to be realized—this is the “philosophy of detail” in semiconductor manufacturing: controlling every tiny contamination to ensure stable chip operation.