JTAG Download Method Summary for Altera FPGA with Nios II Core

1. For Altera FPGA, when using Nios II, there are four types of files that need to be downloaded: .sof file, .pof file, .jic file, and .elf file.

JTAG Download Method Summary for Altera FPGA with Nios II Core

2. The .sof file and .pof file are usually referred to as FPGA “hardware” or “firmware” files, generated by design compilation in Quartus II. The source file formats include VHDL, Verilog HDL, AHDL, Tcl (generally used for pin definitions), schematic (generally used for the top level), etc. The .elf file is a “software” file, generated by design compilation in Nios II IDE (the new version is Nios II Software Builder Tools for Eclipse), with the source file being in C language.

3. The .jic file is a JTAG Indirect Configuration File, generated by converting the .sof file using the Convert Programming File command in the File menu of Quartus II. Then, use the Programmer command under the Tools menu of Quartus II to download it to FLASH (Note: After downloading the .jic file to FLASH, the power must be turned off and then powered back on!). As shown in the figure below:

JTAG Download Method Summary for Altera FPGA with Nios II Core

JTAG Download Method Summary for Altera FPGA with Nios II Core

4. The .elf file cannot be downloaded alone; it must be downloaded together with the “hardware” .sof file to run (it can also be downloaded first in Quartus II, and then the .elf can be downloaded in Nios II IDE or Nios II Software Builder Tools for Eclipse). Taking Quartus II version 11.0 as an example, the method is as follows:

(1) Using Nios II 11.0 IDE

First click “Start | Programs | Altera|Nios II EDS 11.0 | Legacy Nios II Tools | NiosII11.0 IDE” (Note: The “Legacy Nios II Tools” for version 11.0 must be downloaded and installed separately!) to start the Nios II 11.0 IDE, open or import the project, then in Nios II IDE click Tools->Flash Programmer…, and the following interface will appear:

JTAG Download Method Summary for Altera FPGA with Nios II Core

The parts to be checked are marked with a red box in the figure, the first part is to write the software program from Nios II to Flash, and note that the JDI file must also be loaded, i.e., click “Load JDI File” and select the JDI file in this system. The second part is to download the FPGA configuration file to Flash, click “Browse…” to select the .sof file generated by Quartus II, and also select where to download the configuration file, which is still Flash. The last part checked is to validate the Nios II system ID before software download, which means that before downloading the software program, the system’s ID number must be confirmed, so that every time the “hardware” (i.e., .sof file) is modified in Quartus II or the “software” (i.e., .elf file) is modified in Nios II IDE, an alarm prompt will ensure that the hardware and software versions are synchronized.

The unchecked part is to download other files to Flash, such as configuration data files (like the Lince5M181 CMOS camera!), Chinese character library files, waveform files, etc., which are stored directly in Flash and can be read as needed.

After choosing, click “Apply”, then click “Program Flash” to proceed with the Flash burning. If the Console in Nios II IDE shows the following prompt:

#!/bin/sh

………….

Programmed xxxKB +xxxKB in x.xs (xxxKB/s)

Did not attempt to verify device contents

Leaving target processor paused

Then it indicates that the Flash burning was successful, and you can turn off the power and restart it to run.

(2) Using Nios II Software Builder Tools for Eclipse (referred to as Nios II SBT for Eclipse)

Start from the Nios II menu in Altera SOPC Builder, or from “Start | Programs | Altera | Nios II EDS xx.x | …”. Then download the program as follows:

● Select the Flash Programmer from the Nios II menu (Ctrl+7), and the Flash Programmer settings window will pop up:

JTAG Download Method Summary for Altera FPGA with Nios II Core

● Select New from the File menu, and a window will pop up:

JTAG Download Method Summary for Altera FPGA with Nios II Core

● Specify the setting.bsp file, and the sopc information will be loaded automatically.

JTAG Download Method Summary for Altera FPGA with Nios II Core

● Add the .sof file (under the Quartus project) and the .elf file (under the Nios project) respectively.

JTAG Download Method Summary for Altera FPGA with Nios II Core

● Click the Start command to convert, and by default, it will generate two folders, flash and script, under the bsp folder in the software directory, completing the burning process. Power off and restart or reset to complete.

5. For some FPGAs, sometimes after downloading the program to FLASH using the two methods mentioned in 4, it may not run normally after powering on. This seems to be a bug in Altera’s Nios II EDS, which many users have encountered. A solution has been provided in the Altera forum:

(1) Create a new folder at the root directory of the hard disk. For example: D:\jic.

(2) Copy the .sof and .elf files generated by the Quartus II project and Nios II project into this folder;

(3) Create a new sh file in the following format, named xxx.sh; (a sh file is a batch file for bash, similar to DOS’s bat file)

echo "sof>flash …"; sof2flash --epcs --input=demo.sof --output=sof.flash --quiet
echo "elf>flash …"; elf2flash --epcs --after=sof.flash --input=demo.elf --output=elf.flash
echo "cat flash…"; cat elf.flash >> sof.flash
echo "flash>hex…"; nios2-elf-objcopy --input-target srec --output-target ihex sof.flash sof_elf.hex
echo "del flash …"; rm -f *.flash

(4) Run “Start | Programs | Altera | Nios II EDS 11.0 | Nios II 11.0 Command Shell”, and execute:

cd d:\jic

./xxx.sh

(5) In Quartus II, use Convert Programming Files to convert the above command-generated sof_elf.hex into a .jic file, similar to the above method 3, just replace SOF Data with HEX Data (remove first, then add), click Generate to create jic, and then write the jic to Flash.

JTAG Download Method Summary for Altera FPGA with Nios II Core

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