Introduction to Configuring ADC via SPI with FPGA: Analysis of 4-Line SPI Timing

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This article will take Texas Instruments (TI) high-speed ADC chip – ads52j90 as an example to introduce and analyze the 4-line SPI configuration timing of ADC.

From the datasheet of ads52j90, we can easily find that its SPI control module mainly includes 4 signal lines: SEN, SCLK, SDIN, and SDOUT. TI’s naming convention for its product’s SPI configuration signals is different from the general SPI signal naming convention, but in fact, SEN corresponds to CSB, SDIN corresponds to SDI, and SDOUT corresponds to SDO.

• SEN: The enable signal for SPI read and write;

• SDIN: The configuration data written by FPGA to the ADC (register address and corresponding address value);

• SDOUT: The configuration register data output by the ADC corresponding to the address;

• SCLK: The SPI interface clock provided by FPGA to the ADC.

First, we will introduce the write timing of this ADC. The timing diagram provided in the datasheet is shown in Figure 1: We first take a rough look at the write timing diagram, we can understand that for SDIN, it is necessary to write the 8-bit address A7~A0 first, and then write the 16-bit register value D15~D0 at that address, which means that each write operation requires continuous writing of 24 bits of data. For SEN, during the write operation, it remains low, and must be high before and after writing. For SCLK, its rising edge samples the center position of each 1-bit SDIN data, requiring a total of 24 samples to complete the writing of the 24-bit SDIN data.

Figure 1: SPI Write Timing Diagram

The above three points are the conclusions we initially obtained from this timing diagram. For this ADC, writing in this manner will not be a problem. In fact, all ADC’s SPI write operations have similar common principles, summarized as follows:

1. Regardless of whether the SPI is performing read or write operations, SEN must be pulled low; otherwise, SPI will not work (neither read nor write), and SEN must be pulled high after read and write are completed;

2. The data of SDIN must be written to SPI on the rising edge of SCLK;

3. The composition of SDIN data must first write the configuration register address, followed by continuously writing the configuration register value;

Figure 2: SPI Timing Requirements

In addition, we see many timing parameters on the timing diagram. When writing code, we must not only adhere to the above common principles but also meet the timing relationships of these parameters and retain a certain amount of time. The datasheet provides the sizes of these parameters, as shown in Figure 2. For example, the minimum value of t_SCLK is 50ns, which means the maximum SPI clock is 20MHz. The minimum value of t_{SEN_SU} is 8ns, indicating that the falling edge of SEN must be at least 8ns before the first rising edge of SCLK. t_DSU indicates that the data of SDIN must be prepared at least 5ns before the rising edge of SCLK, and so on. As long as the relevant SPI principles and the SPI timing parameters in the datasheet are followed, the SPI write operation will not have any issues.

Now we will introduce the SPI read timing of this ADC, as shown in Figure 3. The main purpose of the read operation is to monitor the internal register status of the ADC to determine whether the ADC’s configuration status meets the user’s needs. From the figure, we can see that the SPI read operation can be decomposed into two parts: the first part is to write the 8-bit register address A7~A0 to SDIN, and then SDOUT outputs the corresponding 16-bit register value.

Here, it is important to emphasize: theoretically, after the last 1-bit address is latched in on the rising edge, on each subsequent falling edge of SCLK, SDOUT outputs 1 bit of register value until the 16-bit register value is fully output. However, in practice, the data output on each falling edge of SCLK only stabilizes after t_{OUT_DV} (12ns ~28ns), and the backend FPGA can correctly receive it. From the figure, we can see that it is very suitable for the FPGA to acquire the data from SDOUT near the rising edge of SCLK, as the data acquired at this position is the most stable.

Figure 3: SPI Read Timing Diagram

4-line SPI read and write timing analysis ends here, emphasizing several key points again:

Key Point 1: SEN must be pulled low during read and write operations. After read and write are completed, it must be pulled high.

Key Point 2: The data of SDIN must be written to SPI on the rising edge of SCLK. The corresponding data format must be register address + the value to be written to the register.

Key Point 3: The data of SOUT is always output on the falling edge of SCLK, so it is most stable for the FPGA to acquire SDOUT data on the rising edge of SCLK.

Key Point 4: It is essential to meet the SPI timing parameters provided by the datasheet and to leave appropriate timing margins when implementing the code.

This article briefly introduced the 4-line SPI configuration timing of ADC using Texas Instruments (TI) high-speed ADC chip – ads52j90 as an example, hoping we can learn and progress together! The next article will take Analog Device (ADI) multi-channel high-speed ADC chip AD9249 as an example to introduce the 3-line SPI read and write configuration timing.

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