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Currently, most FPGA chips are based on SRAM architecture, and the data in SRAM cells will be lost when powered off. Therefore, after the system is powered on, the correct configuration data must be loaded into SRAM by the configuration circuit, after which the FPGA can operate normally.
Common configuration chips include EPCS chips (EPCS4, EPCS8, EPCS16, EPCS64, EPCS128), as well as general serial SPI FLASH chips such as M25P40, M25P16, W25Q16, etc.
Configuration is the process of programming the contents of the FPGA.It is a characteristic, or can be said to be a disadvantage, of SRAM-based FPGAs that configuration is required after each power-up.The FPGA configuration process is as follows:
FPGA Configuration Methods
Based on the role of the FPGA in the configuration circuit, the configuration methods can be divided into three categories:
1. FPGA Active Serial (AS) Method
2. JTAG Method
3. FPGA Passive Method
FPGA Configuration Process
The FPGA configuration includes three stages: Reset, Configuration, and Initialization.
After the FPGA is powered on, when its nCONFIG pin is pulled low, the device is in a reset state, at which point all configuration RAM contents are cleared, and all I/O are in high-impedance state. The FPGA’s status pins nSTATUS and CONFIG_DONE will also output low.When a low-to-high transition occurs on the FPGA’s nCONFIG pin, configuration begins, and the chip will sample the signal state of the configuration mode (MSEL) pin to determine which configuration mode to accept.
Subsequently, the chip will release the open-drain output of the nSTATUS pin, allowing it to be pulled high by an external pull-up resistor, indicating that the FPGA can receive configuration data.During and prior to configuration, the FPGA’s user I/O are all in high-impedance state.
During the reception of configuration data, the configuration data is sent in through the DATA pin, while the configuration clock signal is sent in through the DCLK pin. The configuration data is latched into the FPGA on the rising edge of DCLK, and once all configuration data has been loaded into the FPGA, the CONF_DONE signal on the FPGA will be released, and the open-drain output of the CONF_DONE signal will also be pulled high by an external pull-up resistor.Thus, the low-to-high transition of the CONF_DONE pin indicates the completion of configuration and the beginning of the initialization process, rather than the chip starting to operate normally.
INIT_DONE is the signal indicating the completion of initialization, which is an optional signal in the FPGA and needs to be set through the Quartus II tool to decide whether to use this pin.During the initialization process, internal logic, internal registers, and I/O registers will be initialized, and the I/O drivers will be enabled.
Once initialization is complete, the INIT_DONE pin, which outputs from the device, is released and pulled high by an external pull-up resistor.At this point, the FPGA fully enters user mode, and all internal logic and I/O operate according to the user’s design, at which point the weak pull-up of I/O during the FPGA configuration process will no longer exist.However, some devices still have programmable weak pull-up resistors on I/O in user mode.After configuration is complete, the DCLK signal and DATA pin should not be floating but should be pulled to a fixed level, either high or low.
FPGA Configuration Mode Selection
Users can select the configuration method by setting the states of the MSEL0 and MSEL1 pins on the FPGA.The settings for various methods of MSEL0 and MSEL1 are listed in the table below:
Note:
In the table above, if only one configuration method is used, MSEL0 and MSEL1 can be directly connected to VCC (note that it must be the same as the power supply VCCIO of the FPGA’s IO ports) or GND;
If multiple configuration methods are needed, then MSEL must be controlled by a controller (such as a microcontroller or CPLD) for switching;
The MSEL pins must be in a fixed state before configuration begins, so they cannot be left floating.
Active Serial Configuration
The Active Serial configuration method (AS) stores the configuration data in a serial configuration device EPCS in advance, and then when the system is powered on, the Cyclone IV FPGA reads the configuration data through the serial interface (if it is compressed data, it will also be decompressed) to configure the internal SRAM cells.
Because the FPGA controls the configuration interface in the above configuration process, it is usually referred to as the active configuration method.During configuration, the Cyclone IV uses the serial interface to read configuration data to program the internal SRAM.The four interfaces of the serial configuration device include: serial clock input DCLK, serial data output DATA, active low chip select signal NCE, and serial data input ASDI.
Active Serial configuration circuit diagram:
Because the nSTATUS and CONFIG_DONE pins on the FPGA are open-drain structures, they must be connected to pull-up resistors.The chip select pin nCE of the FPGA must be grounded.
JTAG Configuration
Through the JTAG interface, the Quartus II software can directly reconfigure the FPGA hardware.Quartus II software automatically generates a .sof file for JTAG configuration during compilation.
If both AS and JTAG methods are used to configure the FPGA, JTAG configuration has the highest priority, at which point the AS method will stop and the JTAG method will be executed.
Using Quartus II software and USB Blaster or other download cables can download configuration data to the FPGA.Quartus II software can verify whether JTAG configuration is successful.JTAG configuration directly configures the FPGA using SOF, Jam, or JBC files through the download cable, and this configuration method can only be used during the debugging phase, as the configuration data in the FPGA will be lost after power-off.
Passive Serial Configuration
The passive serial PS configuration method is a commonly used configuration method for the Altera Cyclone IV series FPGA.However, in engineering applications, if this configuration method is used, the FPGA needs to be connected to an intelligent host (such as a complex programmable logic device CPLD/microcontroller MCU, etc.) to provide the configuration clock and configuration data.
In this configuration method, the intelligent host only needs to provide a DCLK signal and a DATA0 signal to configure the FPGA while ensuring correct communication with the flash memory that stores configuration data.Additionally, the DCLK signal can achieve various frequencies to meet user demands for configuration time, which is a highlight of this configuration method.
This article introduces the power-up process of FPGA chips using Altera as an example and describes three common configuration modes. Users can choose the corresponding configuration mode based on different needs, and the types of configuration data corresponding to each configuration mode are also different.
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