Currently, there is an ADC connected to the FPGA, and the first step to achieve high-speed data reading on the FPGA is to ensure reliable hardware connections. It is important to note:

1. Pay attention to signal integrity and try to avoid edge degradation; these two concepts are distinct:

i. High-speed signals refer to signals that transition from high to low or vice versa in a very short time; a 1MHz TTL signal or LVDS signal can be considered high-speed as long as the edges are sufficiently steep!

ii. High-frequency signals generally refer to signals with a sufficiently short period;

iii. Therefore, high-speed signals are not necessarily high-frequency; digital signals are generally high-speed signals, so it is essential to ensure the integrity of their edges. If the edges degrade or distort, it will introduce additional timing deviations;

2. Maintain equal lengths for clock signals and data signal paths, regardless of whether they are single-ended or differential signals. Use routing to force the two types of lines to be nearly equal in length; this is very important in previous timing analysis. If it is impossible to achieve equal lengths, or if the difference is significant, the difference must be obtained in advance and synthesized as timing differences, which will be useful in subsequent timing analysis;

Once the above two points are ensured, we can start timing analysis. The first step is to obtain the timing of the target device ADC, as shown in the figure below:

Figure 1 Timing diagram of a certain ADC

From the above figure, we first obtain several pieces of information:

1. This is synchronous timing, consisting of two types of signals: clock signal DCO and data signals FCO and D (ignoring that they are differential signals; the following analysis will simplify them to single-ended signals for easier illustration).

2. This is a DDR signal, where DDR refers to data synchronized with the rising and falling edges of the clock signal, so this type of synchronous signal requires the introduction of the concept of a virtual clock, which will be introduced later;

3. The signals are not edge-aligned but are offset by 90 degrees! In other words, after the DCO edge transitions, the data signal does not transition immediately but is delayed by a quarter of a cycle. This delay is a common technique used in high-speed signals, and we will find that this delay makes timing analysis easier;

Disregarding the actual significance of the FCO signal and D signal, from the designer’s perspective, they are simply data. The simplified timing diagram is shown below:

Figure 2 Simplified timing diagram

It can be seen that all data signals are actually synchronized to the edges of DCO, but they are not aligned and are offset by 90 degrees, while still being a DDR system (both edges are Launch Edges).

Generally, DDR systems introduce the concept of a virtual clock, meaning that DCO is the actual existing clock, and a virtual clock DCOX2 is created with double the frequency and shifted by 180 degrees. We obtain the following diagram:

Figure 3 Data timing diagram after introducing the virtual clock

After introducing the virtual clock, we re-plan the Launch Edge to align with the rising edge of DCOX2-Shift180, while the corresponding Latch Edge remains on DCO.

So far, we have clearly planned the relationship between the ADC’s clock and data outputs. As for how to describe this using SDC language, see below; we now need to consider that these signals actually arrive at the FPGA pins after passing through PCB traces, and then enter the FPGA and go through their respective internal FPGA routing delays before reaching their target registers, as shown in the figure below:

Figure 4 Simplified signal flow diagram of ADC and FPGA

From the above figure, we can ascertain:

1. The ADC appears to have a source clock, the generation of which we need not concern ourselves with. It is divided into two paths, one of which triggers REG0 on the ADC after frequency doubling and phase shifting (meaning its rising edge serves as the Launch Edge), while the other path directly outputs to the ADC pin DCO;

2. Data generated by REG0 is output to the ADC pin D, which after a delay reaches the corresponding input pin D` of the FPGA. Meanwhile, the DCO pin also reaches the FPGA’s input pin DCO` via PCB;

3. After entering the FPGA, these two signals each split into two paths, respectively going through their own delays to reach their targets:

a) The DCO` pin input goes through TCLK2 to reach the clk pin of REG1;

b) The DCO` pin input goes through TCLK3 to reach the clk pin of REG2;

c) The D` pin input goes through Tdata2 to reach the D pin of REG1;

d) The D` pin input goes through Tdata3 to reach the D pin of REG2;

4. REG1 and REG2 differ; one is triggered on the rising edge, while the other is triggered on the falling edge (a small circle is added before the clk), because the latch edge is originally on the rising edge and has a falling edge; in the future, a virtual clock could also be introduced for DCO`, but that won’t be discussed here;

5. Regardless of whether REG1 or REG2 is used, to latch the data, it must meet the setup time and hold time, which is also reflected in the following diagrams;

As much as has been said, nothing is more practical than the actual timing diagram. Here are the diagrams:

Figure 5 Actual timing analysis

The above diagram shows three colored timings, respectively:

1. The purple line represents DAT, which is the data arrival time, composed of Tco (not shown in the diagram, can refer to the manual), Tdata1, and Tdata2. Does this differ from our DAT definition? The formula is fixed; it only needs to be understood in context. Compared to the formula, it lacks Tclk (the delay from the source clock to the clk of REG0), because we do not need to consider this delay. We are deducing the internal structure from the timing diagram of the ADC data manual, so all delays have already been reflected or combined in the deduction process!

2. The green and brown lines express two meanings: DRTsu and DRTh, representing the required time for data setup and the required time for data hold;

3. By subtracting the two as defined, we can obtain the setup time margin and hold time margin!

As shown in the diagram, within the time window defined by the brown line, REG1.D has already received new data, and there is no change in this time window, thus satisfying both the conditions of setup time margin > 0 and hold time margin > 0. This timing is stable!

However, this is merely a representation. All Tdata1, Tdata2, Tdata3, and Tclk1, Tclk2, Tclk3 are currently assumed. In actual constraints, those values need to be defined by the designer, while others are automatically generated. What are those values?

1. Tdata1 and Tclk1 are determined by the actual PCB routing; if equal-length routing rules are followed, the two can cancel each other out;

2. The timing of DCO and DCOX2-shift180 is determined by the device;

3. Tdata2, Tdata3, Tclk2, and Tclk3 are automatically generated by the FPGA during routing!

Thus, we only need to inform the FPGA of the timing relationship between DCO` and D`. To obtain the timing relationship between the two, we must first understand the original relationship between DCO and D, and how they are affected by routing delays to become DCO` and D; how do we describe the relationships mentioned above? By using an SDC file!

In other words, the SDC file must accurately inform the FPGA of what the input (we won’t consider outputs for now) signals will look like when they enter the FPGA. Based on this information, the FPGA will automatically route so that REG1 and REG2 can receive the correct data. If the timing relationships described in the SDC file are extremely poor, it will lead to a scenario where no matter how the FPGA optimizes routing and layout, it cannot achieve correct timing; thus, an error will be output. This will be detailed in future articles on TimeQuest TA; now let’s start writing the SDC file;

# Set various delay constants

# Here we assume the delays on the ADC chip are all 0

set ADC_CLKs_max 0

set ADC_CLKs_min 0

Set ADC_CLKd_max 0

set ADC_CLKd_min 0

# Set the delay between the launch edge and valid data according to the ADC manual, here we assume it is X

set ADC_tCO_max X

set ADC_tCO_min X

# Set the delay difference of clock and data signals on the PCB, even if they are equal-length wiring, we can still define two values, allowing the FPGA to route with more pressure, guiding the routing towards an ideal direction,

# respectively:

set ADC_BD_min XX

set ADC_BD_max XX

# Set two clocks, the first clock is DCO, which will be input from the FPGA’s DCO pin.

# The other clock is the virtual clock, which is double the frequency of DCO and has a 180-degree phase shift.

# These two clocks are synchronized, one is real, and the other is virtual!

create_clock -name DCO-period 5-waveform {1.25 3.75} [get_ports {DCO}]

create_clock -name DCO_virtual-period 2.5 -waveform {0 1.25}

# Finally, synchronize all data pins to the rising edge of DCO_virtual, setting input and output delays according to the above delay constants. This statement is crucial; it informs the FPGA of the relationship between all input signals and the clock before entering the FPGA!

set_input_delay -clock DCO_virtual -max [expr $ADC_CLKs_max + $ADC_tCO_max + $ADC_BD_max – $ADC_CLKd_min] [get_ports {D*}]

set_input_delay -clock DCO_virtual -min [expr $ADC_CLKs_min + $ADC_tCO_min + $ADC_BD_min – $ADC_CLKd_max] [get_ports {D*}]

SDC file explanation

1. The blue section defines various delay parameters, which are set based on actual PCB routing or ADC book parameters.

2. The green section sets synchronous clocks, and if necessary, virtual clocks;

3. The purple section synchronizes all input signals to the clock. In this case, this clock is a virtual clock because we assume the rising edge of the virtual clock is the launch edge. It could also be synchronized to DCO, but that would require setting it to synchronize with the falling edge, which would be more cumbersome; however, both can be achieved!

Through the above statements, the FPGA understands the relationships between the signals: the relationship between D and DCO, and the relationship between D and DCOX2-shift180 (which is DCO_Virtual);

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