14.5.1
ELC Block Diagram Analysis
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Events can be linked to the following module functions:
Table 2: Module Functions
Chapter 15
ICU – External Interrupts
References for this Chapter
“RA6M5 Group User’s Manual: Hardware”
Main Reference Chapter: 13. Interrupt Controller Unit (ICU)
15.1
External Pin Interrupts
In the previous chapter, we detailed the NVIC, ICU, ELC, and NMI, providing a comprehensive understanding of the interrupt management system in the RA series MCUs. This chapter focuses on how to control external interrupts, which is also an instance application of the NVIC within the core, representing a crucial external interrupt resource for the RA series MCUs.
15.1.1
ICU Block Diagram – Introduction to External Interrupts
Click to view the full image
According to the functional block diagram of the ICU, we first need to configure the IRQCR register (IRQ Control Register, where IRQ stands for Interrupt ReQuest). Next, we configure the IELSR register (ICU Event Link Setting Register). After that, we enable the IR register. Finally, we need to configure the NVIC; details about the NVIC can be found in the previous section.
15.1.2
Introduction to Relevant Registers
15.1.2.1
Introduction to IRQCR
The Interrupt Request Control Register (IRQCR) has 0-15 channels and three flag bits:
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IRQMD[1:0] Detection Sensitivity Selection
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FCLKSEL[1:0] Digital Filter Sampling Clock Selection
-
FLTEN Digital Filter Enable
IRQ Control Register:
Table 1: IRQCRi Register
Table 2: IELSR Register
The Interrupt Control Unit Event Link Setting Register (IELSRn) has a total of 96 instances in the entire RA6M5.
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To be continued
Recommended Reading
Simple Software Delay Function – Practical Guide to Developing with Renesas RA Series FSP Library (34)
Overview of Interrupt Applications in RA Series MCUs – Practical Guide to Developing with Renesas RA Series FSP Library (35)
NVIC Interrupt Configuration Firmware Library & RA6M5 – Practical Guide to Developing with Renesas RA Series FSP Library (36)
