Numerous application cases of Industrial, Scientific, and Medical Radio Frequency (ISM-RF) products indicate that the printed circuit board (PCB) layout of these products can easily exhibit various defects. It is often found that the same IC installed on two different circuit boards can show significant differences in performance metrics. Variations in operating conditions, harmonic radiation, anti-interference capability, and startup time all illustrate the importance of PCB layout in a successful design.
This article lists various design oversights, discusses the reasons for circuit failures caused by each mistake, and provides suggestions on how to avoid these design flaws. The article takes a double-sided PCB with FR-4 dielectric and a thickness of 0.0625in as an example, with the circuit board’s bottom layer grounded. The operating frequency ranges between 315MHz and 915MHz, with Tx and Rx power levels between -120dBm and +13dBm. Table 1 lists some potential PCB layout issues, their causes, and their effects.
Table 1. Typical PCB Layout Issues and Effects
|
Problem |
Cause |
Effect |
|
LNA/tank circuit arrangement (receiver) |
Inductor orientation |
RF feedthrough |
|
Degeneration/π-network arrangement (transmitter) |
Inductor orientation |
RF feedthrough |
|
Shared ground vias between legs of π network |
Via parasitics |
Feedthrough, RF leakage |
|
Shared ground vias between receiver blocks |
Via parasitics |
Crosstalk, RF feedthrough, RF leakage |
|
Long traces for decoupling capacitors |
Higher-impedance connections |
Reduced decoupling |
|
Wide component placement |
Increased parasitics, ground loops |
Detuning, crosstalk, feedthrough |
|
Colinear traces in the transmitter circuit |
Filter bypassing, i.e., power amplifier(PA) directly to antenna |
Harmonics radiation |
|
Top-layer copper pours |
Parasitic coupling |
RF leakage, RF interference |
|
Discontinuous ground plane |
Return current concentration |
Crosstalk, feedthrough |
|
Crystal connection trace length |
Excess capacitance |
LO frequency pulling |
|
Crystal connection trace separation |
Excess capacitance |
LO frequency pulling |
|
Ground plane under crystal pads |
Excess capacitance |
LO frequency pulling |
|
Planar PCB trace inductors |
Poor inductance control |
Most of these issues stem from a few common causes, which we will discuss one by one.
Inductor Orientation
When two inductors (or even two PCB traces) are placed close to each other, mutual inductance occurs. The magnetic field generated by the current in the first circuit will induce a voltage in the current of the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the induced voltage is determined by the mutual inductance LM:
Where YB is the error voltage injected into circuit B, and IA is the current 1 acting on circuit A. LM is very sensitive to the spacing between circuits, the area of the inductive loop (i.e., magnetic flux), and the direction of the loop. Therefore, the best balance between a compact circuit layout and reduced coupling is to correctly arrange the orientation of all inductors.
Figure 1. Mutual inductance is related to the orientation of inductors as shown by the magnetic field lines
Adjust the direction of circuit B to make its current loop parallel to the magnetic field lines of circuit A. To achieve this, try to arrange the inductors to be perpendicular to each other. Refer to the layout of the low-power FSK superheterodyne receiver evaluation (EV) board (MAX7042EVKIT) (Figure 2). The three inductors (L3, L1, and L2) on this circuit board are placed very close together, arranged at 0°, 45°, and 90°, which helps to reduce mutual inductance between them.
Figure 2. The image shows two different PCB layouts, one with an unreasonable component orientation (L1 and L3), and another with a more appropriate orientation.
In summary, the following principles should be followed:
Inductors should be spaced as far apart as possible.
Inductor orientations should be at right angles to minimize crosstalk between inductors.
Lead Coupling
Just as the orientation of inductors affects magnetic field coupling, if leads are too close to each other, it can also affect coupling. This layout issue can also produce what is known as mutual inductance. One of the main concerns in RF circuits is the routing of sensitive components in the system, such as input matching networks, resonant paths of receivers, and antenna matching networks of transmitters.
The return current path should be as close as possible to the main current path to minimize the radiated magnetic field. This layout helps to reduce the area of the current loop. The ideal low-resistance path for return current is usually the grounding area beneath the leads—effectively limiting the loop area to the area of the dielectric thickness multiplied by the lead length. However, if the grounding area is segmented, it will increase the loop area (Figure 3). For leads that cross the segmented area, the return current will be forced through a high-resistance path, greatly increasing the area of the current loop. This layout also makes the circuit leads more susceptible to mutual inductance effects.
The image shows that a complete large-area ground helps improve system performance
For an actual inductor, the orientation of the leads has a significant impact on magnetic field coupling. If the leads of sensitive circuits must be close to each other, it is best to arrange the lead orientations vertically to reduce coupling (Figure 4). If vertical arrangement is not possible, consider using guard traces. For the design of guard traces, please refer to the following sections on grounding and filling treatment.
Figure 4. Similar to Figure 1, indicating potential magnetic field coupling.
In summary, the following principles should be followed when laying out the board:
Ensure complete grounding beneath the leads.
Sensitive leads should be arranged vertically.
If leads must be arranged in parallel, ensure sufficient spacing or use guard traces.
Ground Vias
The main issues in RF circuit layout often stem from the non-ideal characteristic impedance of the circuit, including circuit components and their interconnections. If the copper layer of the leads is thin, it is equivalent to an inductive line and forms distributed capacitance with adjacent leads. When leads pass through vias, they also exhibit inductive and capacitive characteristics.
Via capacitance mainly arises from the capacitance formed between the copper on the via pad and the ground layer copper, separated by a relatively small annulus. Another influence comes from the cylindrical shape of the metal via itself. The effect of parasitic capacitance is generally small and usually only causes degradation of the edges of high-speed digital signals (this article does not discuss this).
The maximum impact of vias is the parasitic inductance caused by the corresponding interconnection method. Because in RF PCB design, most metal via sizes are similar to the sizes of lumped components, a simple formula can be used to estimate the impact of circuit vias (Figure 5):
Where LVIA is the lumped inductance of the via; h is the height of the via in inches; d is the diameter of the via in inches.
Figure 5. Via structure used to estimate parasitic effects in PCB cross-section
Parasitic inductance often has a significant impact on the connection of bypass capacitors. An ideal bypass capacitor provides a high-frequency short circuit between the power layer and the ground layer; however, non-ideal vias can affect the low-inductance path between the ground layer and the power layer. A typical PCB via (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductance. Given the specific operating frequency of ISM-RF products, vias can adversely affect sensitive circuits (e.g., resonant paths, filters, and matching networks).
If sensitive circuits share vias, such as the two arms of a π network, other issues can arise. For example, placing an ideal via equivalent to lumped inductance, the equivalent schematic will differ significantly from the original circuit design (Figure 6). Similar to crosstalk from shared current paths, this leads to increased mutual inductance, increasing crosstalk and feedthrough.
Figure 6. Comparison of ideal and non-ideal architectures, with potential “signal paths” present in the circuit.
In summary, circuit layout needs to follow the following principles:
Ensure modeling of via inductance for sensitive areas.
Use independent vias for filters or matching networks.
Note that thinner PCB copper will reduce the impact of via parasitic inductance.
Lead Length
Maxim ISM-RF product data sheets often recommend using the shortest possible high-frequency input and output leads to minimize losses and radiation. On the other hand, such losses are often caused by non-ideal parasitic parameters, so parasitic inductance and capacitance will affect circuit layout, and using the shortest leads helps to reduce parasitic parameters. Typically, a 10 mil wide PCB lead, 0.0625in from the ground layer, if using an FR4 circuit board, will produce approximately 19nH/in of inductance and about 1pF/in of distributed capacitance. For LAN/mixer circuits with 20nH inductance and 3pF capacitance, a very compact layout of circuits and components can significantly affect the effective component values.
The IPC-D-317A4 from the “Institute for Printed Circuits” provides an industry-standard equation for estimating various impedance parameters of microstrip line PCBs. This document was replaced by IPC-2251 in 2003, which provides more accurate calculation methods for various PCB leads. Online calculators based on the equations provided by IPC-2251 can be obtained through various channels. The Electromagnetic Compatibility Laboratory at Missouri University of Science and Technology offers a very practical method for calculating PCB lead impedance.
The recognized standard for calculating microstrip line impedance is:
Where εr is the dielectric constant of the dielectric, h is the height of the lead from the ground layer, w is the lead width, and t is the lead thickness (Figure 7). The formula is quite accurate when w/h is between 0.1 and 2.0, and εr is between 1 and 15.
Figure 7. This figure shows the PCB cross-section (similar to Figure 5), indicating the structure used to calculate microstrip line impedance.
To assess the impact of lead length, it is more practical to determine the de-tuning effect of lead parasitic parameters on the ideal circuit. In this example, we discuss stray capacitance and inductance. The standard equation for characteristic capacitance used for microstrip lines is:
Similarly, the characteristic inductance can be calculated from the above equation:
For example, assuming a PCB thickness of 0.0625in (h = 62.5 mil), 1 oz copper lead (t = 1.35 mil), width of 0.01in (w = 10 mil), using an FR-4 circuit board. Note that the typical εr value for FR-4 is 4.35 F/m, but can range from 4.0 F/m to 4.7 F/m. The calculated characteristic values are Z0 = 134Ω, C0 = 1.04pF/in, L0 = 18.7nH/in.
For ISM-RF designs, leads with a layout length of 12.7mm (0.5in) on the PCB can produce approximately 0.5pF and 9.3nH of parasitic parameters (Figure 8). This level of parasitic parameters can affect the resonant path of the receiver (variation in LC product), potentially causing a change of 315MHz ±2% or 433.92MHz ±3.5%. Due to the additional capacitance and inductance caused by lead parasitic effects, the peak oscillation frequency for 315MHz reaches 312.17MHz, and for 433.92MHz, it reaches 426.61MHz.
The image shows a compact PCB layout where parasitic effects can impact the circuit.
Another example is the resonant path of Maxim’s superheterodyne receiver (MAX7042), where the recommended components at 315MHz are 1.2pF and 30nH; at 433.92MHz, they are 0pF and 16nH. Using the equation to calculate the oscillation frequency of the resonant circuit:
Evaluation board resonant circuits should include the parasitic effects of packaging and layout, calculating the resonant frequency at 315MHz with parasitic parameters of 7.3pF and 7.5pF. Note that the LC product manifests as lumped capacitance.
In summary, the following principles should be followed when laying out the board:
Keep lead lengths as short as possible.
Place critical circuits as close to the components as possible.
Compensate for parasitic effects on critical components based on actual layout.
A few common causes: Grounding and Filling Treatment#e#
Grounding and Filling Treatment
Ground or power layers define a common reference voltage, supplying power to all components of the system through low-resistance paths. This balances all electric fields in this way, creating a good shielding mechanism.
DC current always tends to flow along low-resistance paths. Similarly, high-frequency currents also preferentially flow through the lowest resistance paths. Therefore, for standard PCB microstrip lines above the ground layer, return current attempts to flow into the grounding area directly beneath the leads. As described in the lead coupling section above, segmented grounding areas will introduce various noise, which can increase crosstalk through magnetic field coupling or current convergence (Figure 9).
Figure 9. Maintaining the integrity of the ground layer as much as possible; otherwise, return current can cause crosstalk.
Filling ground, also known as guard traces, is often used in designs where it is difficult to lay continuous grounding areas or where sensitive circuits need shielding (Figure 10). By placing grounding vias at both ends of the leads or along the leads (i.e., via arrays), the shielding effect can be increased. Please do not confuse guard traces with leads designed to provide return current paths, as such layouts will introduce crosstalk.
Figure 10. In RF system design, avoid floating copper traces, especially when copper skin needs to be laid.
Floating copper areas (not grounded) or grounded only at one end will limit their effectiveness. In some cases, they can form parasitic capacitance, altering the impedance of surrounding wiring or creating “potential” paths between circuits, leading to adverse effects. In short, if a copper area (not a circuit signal trace) is laid on the PCB, ensure consistent plating thickness. Floating copper areas should be avoided as they will affect circuit design.
Finally, ensure to consider the impact of any grounding areas near the antenna. Any monopole antenna will consider grounding areas, traces, and vias as part of the system’s balance; non-ideal balanced wiring will affect the antenna’s radiation efficiency and direction (radiation pattern). Therefore, grounding areas should not be placed directly beneath monopole PCB lead antennas.
In summary, the following principles should be followed:
Provide continuous, low-resistance grounding areas as much as possible.
Ground both ends of filling traces and use via arrays as much as possible.
Avoid floating copper traces near RF circuits, and do not lay copper skin around RF circuits.
If the PCB includes multiple ground layers, it is best to lay a grounding via when signal lines cross from one side to the other.
Excess Crystal Capacitance
Parasitic capacitance can cause the operating frequency of the crystal oscillator to deviate from the target value. Therefore, some general guidelines should be followed to reduce stray capacitance from crystal leads, pads, traces, or connections to RF devices.
The following principles should be followed:
Keep the connection between the crystal and RF devices as short as possible.
Keep traces between each other as isolated as possible.
If the parallel parasitic capacitance is too large, remove the grounding area beneath the crystal.
Planar Trace Inductance
It is not recommended to use planar traces or PCB spiral inductors, as typical PCB manufacturing processes have certain inaccuracies, such as width and spacing tolerances, which can significantly affect the precision of component values. Therefore, most controlled and high-Q inductors are wound types. Alternatively, multilayer ceramic inductors can be chosen, and multilayer chip capacitor manufacturers also provide such products. Nevertheless, some designers still choose spiral inductors out of necessity. The standard formula for calculating planar spiral inductance typically uses Wheeler’s formula:
Where a is the average radius of the coil in inches; n is the number of turns; c is the width of the coil core (rOUTER – rINNER) in inches. When c > 0.2a, the accuracy of this calculation method is within 5%.
Square, hexagonal, or other shapes of single-layer spiral inductors can be used. Very good approximation methods can be found for modeling planar inductors on integrated circuit wafers. To achieve this, the standard Wheeler formula is modified to obtain a very suitable estimation method for small sizes and square specifications of planar inductors.
Where ρ is the filling ratio:
; n is the number of turns, dAVG is the average diameter:
For square spirals, K1 = 2.36, K2 = 2.75.
There are many reasons to avoid using this type of inductance; they are often limited by space constraints, leading to reduced inductance values. The main reason to avoid using planar inductors is the restricted geometric dimensions and poor control over critical dimensions, making it impossible to predict inductance values. Additionally, it is difficult to control actual inductance values during PCB production, and inductance tends to couple noise into other parts of the circuit (refer to the lead coupling section above).
In summary, it is advisable to:
Avoid using planar trace inductors.
Use wound chip inductors whenever possible.
Conclusion
As discussed, several common PCB layout traps can cause ISM-RF design issues. However, by paying attention to the non-ideal characteristics of circuits, you can completely avoid these defects. Compensating for these unwanted effects requires proper handling of seemingly trivial matters, such as component orientation, trace length, via arrangement, and the use of grounding areas. By adhering to the above guidelines, you can significantly save time and money wasted on correcting mistakes.
The End
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Editor: Li Dan
Reviewer: Wang Gang
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