As an embedded engineer, the following commonly used communication protocols are often essential knowledge in interviews.
1. UART Protocol
UART (Universal Asynchronous Receiver/Transmitter) is a bidirectional, serial, asynchronous communication bus that can achieve full-duplex communication with just one data receiving line and one data sending line.
Typical serial communication uses three lines: the transmit line (TX), the receive line (RX), and the ground line (GND). For communication to work properly, the TX and RX of both parties must be cross-connected, and GND must be connected.
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Protocol Characteristics
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Asynchronous:
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No shared clock signal line is required.
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Serial:
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Single data line for serial transmission.
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Full Duplex:
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TX (Transmit): The data sending line (output from the perspective of this device).
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RX (Receive): The data receiving line (input from the perspective of this device).
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Point-to-Point:
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The standard UART protocol is designed to connect two devices.
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Data Frame Format
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Start Bit:
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1 bit of logic low (0), indicating the start of a new data frame.
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Data Bits:
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Typically 5, 6, 7, or 8 bits (most commonly 8 bits). These represent the actual data of one byte (or part of a byte) being transmitted.
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The transmission order is usually least significant bit (LSB) first (i.e., bit0 is sent first, and bit7 is sent last).
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Parity Bit:
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Optional, can be 1 bit or none.Used for simple error detection (odd or even parity).
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Odd Parity: The total number of “1” bits in the data bits + parity bit is odd.
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Even Parity: The total number of “1” bits in the data bits + parity bit is even.
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No Parity: The most common choice, which does not include a parity bit.
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Stop Bits:
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Typically 1 bit, 1.5 bits, or 2 bits (most commonly 1 bit).
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Logic high (1), indicating the end of a data frame.
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Provides separation between frames and ensures that the receiving circuit has enough time to reset and prepare to receive the next start bit.
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Idle State:
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When there is no data transmission, both TX and RX lines remain at logic high (1). The falling edge of the start bit pulls the line from idle high to low.
2. IIC Protocol
I²C Protocol (Inter-Integrated Circuit) is a synchronous, half-duplex, multi-master-slave architecture serial communication protocol developed by Philips (now NXP), designed for short-distance low-speed device communication on a board.
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Protocol Characteristics
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Signal Lines: SDA (Serial Data Line) + SCL (Serial Clock Line) (both are bidirectional open-drain outputs)
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Topology: Bus type, multiple devices in parallel, addressed by address
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Communication Mode: Half-duplex, can only send or receive at the same time
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Speed Modes: Standard mode (100 kbps), Fast mode (400 kbps), High-speed mode (3.4 Mbps)
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Addressing Capability: 7-bit address (supports up to 128 devices) or 10-bit address (supports up to 1024 devices)
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Data Frame Format
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Start Condition (START)
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When SCL is high, SDA transitions from high to low
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Slave Address + Read/Write Bit (ADDRESS + R/W#)
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7-bit Address: High 7 bits (MSB first)
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Read/Write Bit::
<span>0</span>= Master writes,<span>1</span>= Master readsExample: EEPROM write operation at address<span>0x50</span>→<span>1010000 0</span>(binary)
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Acknowledge Bit (ACK/NACK)
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ACK: In the 9th clock cycle, the receiver pulls SDA low
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NACK: SDA remains high (indicating an error or end of transmission)
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Data Byte (DATA)
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Each byte is 8 bits (MSB first), followed by ACK/NACK
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Acknowledge Bit (ACK/NACK)
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ACK: In the 9th clock cycle, the receiver pulls SDA low
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NACK: SDA remains high (indicating an error or end of transmission)
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Stop Condition (STOP)
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When SCL is high, SDA transitions from low to high
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Data Arbitration
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Clock Synchronization
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Line and Logic: The SCL line is controlled in parallel by all masters; any device pulling SCL low causes the bus to go low
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Longest Low Level Wins: The master with the longest low level duration determines the low phase period of SCL
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Data Arbitration
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Each master samples the SDA state during the SCL high level
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If the level sent by itself does not equal the actual level on the bus, it immediately exits the competition
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Failure Behavior
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Switch to slave mode, listen to the communication of the master that won the arbitration
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Release control of SCL
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Cache unsent data, wait for the bus to be idle before retrying
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End of Arbitration
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When a master successfully sends data without interruption, it becomes the bus controller
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Releases the bus after sending the STOP condition
3. SPI Protocol
SPI Protocol (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous serial communication protocol developed by Motorola, designed for short-distance communication between chips on a board.
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Protocol Characteristics
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Signal Lines: CS (Chip Select), SCK (Clock Line), MOSI (Master Out Slave In Data Line), MISO (Master In Slave Out Data Line)
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Topology: Master-slave architecture (one master, multiple slaves), addressed by chip select signals
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Communication Mode: Full duplex
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Transmission Speed: Typically 10-100 Mbps
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Data Transmission Timing
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Data Frame Format
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Multi-Slave Mode
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Independent CS: No interference, optimal speed, but requires more IO ports
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Daisy Chain: Only one CS is needed, data is stacked, speed is limited
