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Table of Contents
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00 Project Overview
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01 Synchronization Processing of Asynchronous Clocks
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02 FIFO Design (Part 1)
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03 FIFO Design (Part 2)
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04 Baud Rate Design
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05 Data Reception Section
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06 Data Transmission Section
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07 Simulation Framework
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08 Baud Rate Model and Register Operations
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09 Data Transmission Model
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10 Data Reception Model
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11 Data Comparison and Interrupt Check
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12 Testcase
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13 Common Interview Questions Related to the Project
Functionality
Implement a UART module (Universal Asynchronous Receiver/Transmitter) connected via the APB bus in ARM, including both design and verification parts.
Project Requirements
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The maximum operating frequency of the system clock is 100MHz, and the functional clock is 26MHz.
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Reset functionality for both system and functional clock domains.
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The configuration interface meets the AMBA2.0-APB bus interface timing, with a bus width of 16 bits.
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Data transmission meets general serial port timing, with configurable parity functionality.
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Baud rate meets 115200, or is configurable.
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Receive and transmit FIFO reset can be controlled separately, with configurable trigger depth.
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Data transmission and reception interrupt functionality is configurable.
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Data transmission interval is controllable.
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Includes status indication functionality.
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Includes FIFO data quantity indication functionality.
Framework
Design
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Baud Rate Generation Module
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Generates the receive and transmit baud rate clock based on the functional clock and configuration.
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Data Reception
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Receives data based on the RX baud rate clock, performs parity check, stores data in the RX FIFO, and is read by the CPU via the APB bus. Contains a receive data state machine.
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Data Transmission
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The CPU places the data to be sent into the TX FIFO via the APB bus, and transmits data based on the TX baud rate clock. Contains a transmit data state machine.
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Register Configuration
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Implements APB read/write register functionality, interrupt operations, function selection, module status indication, etc.
Verification
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Baud Rate Generation
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Generates the baud rate clock used in the simulation environment.
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Data Reception
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Data reception model in the simulation environment.
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Data Transmission
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Data transmission model in the simulation environment.
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APB Bus
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APB bus model in the simulation environment, simulating CPU response to interrupts and implementing various functions.
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Data Comparison
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Generates different comparison results based on the comparison of transmitted and received data and timing, facilitating observation of results during simulation.
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Testcase Generation
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Generates different cases through various stimuli or configurations to verify if the functionality meets requirements.
AMBA-APB Protocol
AMBA The AMBA bus is an advanced microcontroller bus architecture developed by ARM, defining a standard for on-chip communication when designing high-performance embedded microcontrollers. AMBA2.0 defines three different buses: AHB, ASB, and APB.
A typical AMBA-based microcontroller consists of a high-performance central bus (AHB or ASB) that supports high-bandwidth external memory, including CPU, on-chip memory, and other direct memory access (DMA) devices. This bus provides a high-bandwidth interface for most transfers between the aforementioned units. There is also a bridge on this high-performance bus to connect to the lower bandwidth APB, which connects most of the system peripherals.
APB
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Interface Signals
PCLK (input): The clock for the APB bus, all transfers are synchronized to its rising edge. PRESETn (input): The reset signal for the APB bus, active low. PADDR (input): The address bus for the APB. PSELx (input): The selection signal for the APB module, active high. This signal selects the module that needs to transfer data over the APB bus. PENABLE (input): The trigger signal for the APB module, indicating the second clock cycle of the APB transfer. PWRITE (input): Write (active high) and read (active low) signal on the APB bus. PWDATA (input): The write data signal on the APB bus, driven by the APB bus bridge. PRDATA (output): The read data signal on the APB bus, driven by the APB module. Notes:
APB bus transfers require two clock cycles.
Input and output are relative to the APB module (slave).
A “write” operation transfers data from the APB bus to the APB module, while a “read” operation transfers data from the APB module to the APB bus.
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APB Write Operation
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The PADDR, PWRITE, PSEL, and PWDATA signals are valid at the same time. If there is only one “write” operation, the above signals last for two cycles. If there are multiple “write” operations (e.g., in Burst mode), PWRITE and PSEL can remain unchanged, while PADDR and PWDATA change every two cycles.
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The PENABLE signal is valid one cycle after PSEL is valid and lasts for one cycle. If there are multiple “write” operations, the PENABLE signal remains low for one cycle and high for one cycle within every two cycles.
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APB Read Operation
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The PADDR, PWRITE, and PSEL signals are valid at the same time. If there is only one “read” operation, the above signals last for two cycles. If there are multiple “read” operations (e.g., in Burst mode), PWRITE and PSEL can remain unchanged, while PADDR changes every two cycles.
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The PENABLE signal is valid one cycle after PSEL is valid and lasts for one cycle. If there are multiple “read” operations, the PENABLE signal remains low for one cycle and high for one cycle within every two cycles.
- The APB module needs to send the required data for the “read” operation to the APB bus during the valid PENABLE period and maintain it for one cycle.
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