Cortex-M0 Interrupt Control and System Control (Part Five)

The OS can support multitasking, performing context switching periodically and handling tasks in parallel architecture. A crash in a single task does not affect the entire system. Context switching requires a timer to interrupt program execution; the SysTick timer can provide the necessary clock pulses, offering a rhythmic “heartbeat” for OS task scheduling.

The SysTick timer, also known as the system tick timer or “heartbeat timer,” is a 24-bit countdown timer that automatically reloads the initial value from the reload register when it counts down to zero. It will run indefinitely as long as the enable bit in the SysTick control and status register is not cleared, even working in sleep mode.

The SysTick timer is bundled in the NVIC to generate SysTick exceptions (exception number: 15), and the priority of the SysTick interrupt can also be set.

It works based on beats, dividing the entire time period into many small time slices, where each task can only run for the length of one time slice at a time. If it times out, it exits to let other tasks run, ensuring that no single task monopolizes the various timing functions provided by the operating system, all of which relate to this tick timer.

When enabled, the timer counts down from the reload value to zero and reloads the value from SYST_RVR in the next clock cycle, then continues to count down in subsequent clock cycles. Writing a zero value to SYST_RVR will disable the counter at the next callback. When the counter reaches zero, the COUNTFLAG status bit is set to 1. Reading SYST_CSR will clear the COUNTFLAG bit to 0. Writing to SYST_CVR will clear the register and COUNTFLAG status bit to 0; writing does not trigger the SysTick exception logic, and reading this register will return its value upon access.

The SysTick timer mainly consists of 4 registers:

In Arm’s official documentation, the four registers are named SYST_CSR, SYST_RVR, SYST_CVR, and SYST_CALIB, but in CMSIS, the naming has been simplified for clarity.

The CSR register uses 4 bits: bit0 is for enabling the timer, setting it to 1 enables the SysTick timer; bit1 controls whether to generate interrupts, setting it to 1 allows interrupts; and bit2 sets the timer’s clock source, setting it to 1 means the timer’s clock source is the main clock, while setting it to 0 means the timer’s clock source is one-fourth of the main clock.

The HCLK source for the SysTick of the MM32F0130 series comes from the AHB bus after hardware division by 4, while FCLK directly comes from the AHB clock bus.

When the SysTick timer counts down from 1 to 0, it sets the COUNTFLAG bit; the following methods can clear it:

The RVR register uses bits 0 to 23, and this value is the initial countdown value of the timer. After enabling the timer, it counts down from the value set here to 0, and once it counts down to 0, it will start counting down again from this value.

The CVR register also uses bits 0 to 23. This is a status register that changes continuously when the timer starts operating, counting down to 0 after obtaining the initial value from the RVR register.

CURRENT: Reading this register returns the current value of the system timer. Writing a value to this register will reset the timer to 0 and clear the COUNTFLAG bit in CTRL.

If the calibration information is unknown, the required calibration value can be calculated based on the processor clock or external clock frequency.

The calibration value register provides a solution: it allows the system to generate a constant SysTick interrupt frequency even when running on different CM0 products. The simplest approach is to directly write the value of TENMS to the reload register, ensuring that SysTick exceptions occur every 10ms, as long as the system limits are not exceeded. If other SysTick exception periods are required, they can be calculated proportionally based on the TENMS value.

Among the four registers of the system timer, SYST_CALIB is the calibration register, which is configured before leaving the factory, so we do not need to consider this register.

Configuring SysTick needs to follow a specific process:

SysTick can be operated in either polling or interrupt mode. The polling program can read the SysTick control and status register to check the COUNTFLAG. If this bit is set, it indicates that the SysTick count has reached 0.

static __IO uint32_t TimingDelay;
void Delay(__IO uint32_t nTime)
{ 
     TimingDelay = nTime;
     while(TimingDelay != 0);
}

void SysTick_Handler(void)
{
     if (TimingDelay != 0x00) 
     { 
       TimingDelay--;
     }
}

int main(void)
{ 
     // SysTick clock is HCLK, interrupt time interval is 1ms
     if (SysTick_Config(SystemCoreClock / 1000)) 
     {
         while (1);
     }
     while(1)
     { 
         Delay(200);//200ms
     }
}

The SysTick timer can also serve other purposes, such as time measurement, timing, or alarms.