Introduction to Cortex-M0+ Core

The ARM Cortex-M0+ is a low-power, high-efficiency ARM processor released by ARM Holdings on March 14, 2012. It is designed for embedded applications with design constraints. It features the smallest silicon area and minimal code size, allowing developers to achieve 32-bit performance at 16- and 8-bit price points. The low gate count of the processor enables its deployment in applications requiring simple functionality.

As the latest member of the ARM Cortex-M processor series, the 32-bit Cortex-M0+ processor is built on a low-cost 90nm low-power (LP) process, consuming only 9μA/MHz, about one-third of mainstream 8-bit or 16-bit processors, while providing higher performance. This combination of low power and high performance offers users still using 8-bit or 16-bit architectures an ideal opportunity to transition to developing 32-bit devices, enhancing the intelligence of everyday devices without sacrificing power and area. This optimized Cortex-M0+ processor is capable of providing ultra-low-power, low-cost microcontrollers (MCU) for a wide range of applications, including home appliances, white goods, medical monitoring, electronic measurement, lighting equipment, and power and automotive control devices.

The Cortex-M0+ integrates a Memory Protection Unit (MPU), single-cycle I/O interfaces, and a Micro Trace Buffer (MTB). The block diagram of the ARM Cortex-M0+ is shown in Figure 1-1.

Figure 1-1 Block Diagram of ARM Cortex-M0+

The ARM Cortex-M0+ core has the following key features:

·ARMv6-M architecture.

·AHB-lite bus interface, von Neumann bus architecture, with optional single-cycle I/O interfaces.

·Thumb/Thumb-2 instruction set support.

·2-stage pipeline.

·Optional 8-region MPU, with sub-regions and background regions.

·Non-maskable interrupts +1 to 32 physical interrupts.

·Wake-up interrupt controller.

·Hardware single-cycle (32×32) multiplication.

·Multiple sleep modes, with integrated Wait For Interrupt (WFI), Wait For Event (WFE), and wake-up from sleep functions, sleep and deep sleep signals.

·Various retention modes provided based on implementation.

·JTAG and Serial Wire Debug ports, with up to 4 breakpoints and 2 watchpoints.

·Optional Micro Trace Buffer.

The key advantages of the ARM Cortex-M0+ MCU are as follows:

·The small core size allows it to serve as a single core in small devices or as an additional embedded core when specific hardware isolation or task partitioning is needed.

·The Cortex-M0+ core does not affect the trade-offs between components of typical MCUs based on I/O, analog, and non-volatile memory. Therefore, when partitioning MCU product lines, bus size (8, 16, or 32-bit) is no longer relevant.

·M0+ microcontrollers are widely used in entry-level applications and provide significant advantages. They meet computational performance requirements, and their basic architecture allows M0+ MCUs to achieve ultra-low power performance in applications with minimal gate counts. The Cortex-M0 core can reduce noise emissions and meet performance requirements using optimal clock speeds.

·The dynamic power of the core ranges from 5 to 50µW/MHz, depending on the technology used. However, the core does not represent the overall power consumption of the device and is not the only factor to consider.

·The Thumb instruction set is a subset of the Cortex-M series. It allows for the reuse of any verified Cortex-M product software blocks to simplify the scalability of the product line.

·The Memory Protection Unit (MPU) manages CPU access to memory, ensuring that tasks do not accidentally corrupt memory or resources used by other active tasks. The MPU is typically controlled by an RTOS. If a program accesses a memory location prohibited by the MPU, the RTOS can detect this and take action. The core can dynamically update the settings of the MPU region based on the executing process. The MPU is optional and can be bypassed.