Click the blue "Arm Selected" at the top left, and choose "Set as Favorite"9 L2 Memory System
The L2 memory system of the Cortex-A720 core connects the core to the DynamIQ Shared Unit-120 via the CPU bridge, which includes private L2 caches.
The L2 cache is unified, with each Cortex-A720 core having a private L2 cache within a cluster.
The L2 memory system includes a data prefetch engine that uses virtual addresses (VA) and program counters (PC). Different engines can prefetch data into the L2 cache.
The following table shows the characteristics of the L2 memory system.
9.1 L2 Cache
The integrated L2 cache handles instruction and data requests from both the instruction and data sides, as well as translation table walk requests.
The L1 instruction cache and L2 cache are weakly inclusive. Instruction fetches that miss in the L1 instruction cache are allocated to both caches, but invalidation of the L2 cache does not cause a reverse invalidation of the L1 instruction cache.
The L1 data cache and L2 cache are strictly exclusive. Any data contained in the L1 data cache will not exist in the L2 cache. Unless the core power mode is initialized to Debug Recovery Mode, the L2 cache will automatically invalidate on reset.
The way cache index is determined means there is no direct relationship between physical addresses (PA) and set numbers. Targeted operations that assume a relationship between PA and set numbers cannot be used. To flush the entire cache, group and way maintenance operations must be performed according to the number of groups and ways described by the cache’s CCSIDR_EL1. This operation complies with the Armv8-A architecture.
9.2 Memory Type Support
The Cortex-A720 core simplifies consistency logic by downgrading certain memory types:
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Memory marked as Inner Write-Back Cacheable and Outer Write-Back Cacheable will be cached in the L1 data cache and L2 cache. -
Memory marked as Inner Write-Through will be downgraded to Noncacheable. -
Memory marked as Outer Write-Through or Outer Non-cacheable will be downgraded to Noncacheable, even if the inner attribute is Write-Back Cacheable.
Additional attribute hints for operations are as follows:
Allocation Hint
The allocation hint helps determine the allocation rules for newly acquired lines in the system.
Transient Hint
All cacheable reads and writes with the Transient bit set will allocate to the L2 cache. Reads with the Transient bit set that allocate to the L1 data cache will allocate to the L1 cache.
Transient lines evicted from the L1 cache will not allocate to downstream caches.
9.3 Transaction
The interface between the Cortex-A720 core L2 memory system and the DynamIQ™ Shared Unit-120 provides the core with Transaction capabilities.
The following table shows the maximum possible values for reads, writes, Distributed Virtual Memory (DVM) issuance, and snooping capabilities of the Cortex-A720 core L2 cache.
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