AMD’s New EPYC Processor Completes Tape-Out, Utilizing TSMC’s 2nm Process

AMD's New EPYC Processor Completes Tape-Out, Utilizing TSMC's 2nm Process

On April 14 local time, AMD announced that its next-generation Zen 6 EPYC processor “Venice” has officially completed tape-out, becoming the industry’s first high-performance computing (HPC) processor to utilize TSMC’s 2nm (N2) process technology. AMD stated that this marks a significant breakthrough in the collaboration between AMD and TSMC on advanced process technology, demonstrating both parties’ commitment to driving innovation in semiconductor technology.

AMD also announced that its fifth-generation EPYC (Milan) processor has successfully entered production and been validated at TSMC’s Arizona Fab 21.

It is understood that TSMC’s N2 process is its first technology based on Gate-All-Around (GAA) nanosheet transistors. The company expects that compared to the previous generation N3 (3nm), this process technology will reduce power consumption by 24% to 35%, or improve performance by 15% under constant voltage, while also increasing transistor density by 1.15 times. These improvements are primarily attributed to the new transistor design and the N2 NanoFlex design technology’s collaborative optimization framework.

TSMC Chairman and CEO C.C. Wei stated: “We are honored that AMD has become a major HPC customer for TSMC’s advanced 2nm (N2) process technology and TSMC’s Arizona fab. Through our collaboration, both parties are driving significant technological upgrades to enhance the performance, energy efficiency, and yield of high-performance chips. We look forward to continuing our close cooperation with AMD to usher in the next era of computing.”

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