6. Serial Interface Parallel Communication and Serial Communication Asynchronous and Synchronous Communication Asynchronous Serial Full Duplex (P3.0-RXD P3.1-TXD) Timer 1 serves as the baud rate generator to control the rhythm of opening the door, generating transmission and reception completion interrupts TI, RI Mode 0 is used for expanding IO, while Modes 1-2 are communication modes. … Read more
Commonly used microcontrollers for industrial-grade equipment can be broadly divided into HC32L110C6PA-TSSOP20TR and HC32L136K8T6-LQFP64, both produced by Holtek. 1. HC32L110C6PA-TSSOP20TR Core Architecture: 32-bit ARM Cortex-M0+ core Maximum Clock Frequency: 48MHz Memory: Flash 64KB, SRAM 8KB Pin Count: 20 pins (TSSOP package) Operating Voltage: 2.4V ~ 3.6V Peripheral Interfaces: UART, SPI, I2C, ADC (12-bit resolution), Timer, … Read more
Environment: Vivado 2023.2 FPGA Model: XCVU47P FPGA Project Overview: The main control logic of the FPGA uses four AXI interfaces with on-chip HBM resources (supporting up to 16 groups); Main clock domain frequency: 250MHz HBM interface clock frequency: 450MHz Problem: As the number of logic resources and BRAM used in the design increases, timing closure … Read more
Mean filtering is a fundamental digital signal processing technique commonly used for image and signal denoising. This article will detail how to implement a simple yet efficient mean filter using the Verilog hardware description language. Basic Principles of Mean Filtering The core idea of mean filtering is to replace the value of a pixel with … Read more
Table of Contents Hello-FPGA CoaXPress 2.0 Host FPGA IP Core Linux Demo 4 1 Description 4 2 Device Connection 7 3 VIVADO FPGA Project 7 4 Debugging Instructions 10 Figure 1-1 Document Directory 4 Figure 1-2 VIVADO Project Directory Structure 5 Figure 1-3 SDK Project Directory Structure 5 Figure 1-4 Device Tree Information 6 Figure … Read more
Welcome to leave a message, I will reply to each message on the same day, and any errors in the article will be updated in the reply. The design is conducted in the Vivado 2018.3 environment, with specific code and detailed line-by-line comments at the end. This is a dynamic display design for FPGA seven-segment … Read more
Introduction As medical technology continues to evolve, endoscopic examination has become an indispensable method in the diagnosis and treatment of various diseases. From screening gastrointestinal diseases to observing pulmonary lesions and diagnosing urinary system disorders, endoscopes can penetrate deep into the human body, providing doctors with intuitive internal tissue images, significantly enhancing diagnostic accuracy and … Read more
In 2025, a low-key yet monumental invention in the semiconductor industry—FPGA (Field Programmable Gate Array)—will celebrate its fortieth anniversary. This is not just a milestone in time, but rather a dramatic historical metaphor. In this special year of turning forty, the two giants that once dominated the FPGA market for decades, Xilinx and Altera, after … Read more
ASIC Application-Specific Integrated Circuit. An ASIC is designed for a specific application, optimized for a particular task or function, but its wiring and connections are fixed and cannot be changed. For example, Bitcoin mining chips and mobile image processing units. CPU Handles general tasks. A CPU operates using SIMD (Single Instruction, Multiple Data), which is … Read more
Click the blue text above to follow us 01 Basic Overview Acceleration Card Model: Inspur YPCB_00338_1P1 FPGA Chip Model: XC7K480TFFG1156-2 FLASH Chip Model: MT28GU512AAA1EGC-0SIT VIVADO Version: Vivado 2019.2 02 Program Burning In formal engineering projects, after generating the bitstream and verifying the solution, users will burn the official version of the program into FLASH. This … Read more