Intelligent connected vehicles have become a key trend leading future development. Among them, chips, as the core components of intelligent connected vehicles, have increasingly highlighted the importance of their functional safety and reliability. How to enhance their assurance has become a focal topic of concern in the industry. Currently, the market scale of intelligent connected … Read more
In terms of chips, Huawei has always insisted on independent research and development, especially for core high-end chips, such as the Kirin series, Balong series, Kunpeng series, and Lingxiao series. However, after the rules regarding chips were modified, Huawei’s self-developed Kirin 9000 and other chips could not be produced temporarily, because TSMC and others could … Read more
Red Semiconductor has announced the launch of a multifunctional intrinsic structured computing (VISC) architecture for RISC-V. VISC is an extension of RISC-V IP that accelerates complex algorithms and adds parallel processing to improveedge computing‘s AI operations. Red Semiconductor’s CEOJames Lewis. One of the strong value points of RISC-V is the potential for customization within the … Read more
Article Title: RISC-V Word Load Instruction Optimization Based on Linker All Authors: Wu Xinlong, Liao Chunyu First Affiliation: Institute of Software, Chinese Academy of Sciences Publication Date: 2022, 31(9): 24–30 Abstract Abstract RISC-V, as a representative of reduced instruction set computing, also reflects some of the drawbacks of reduced instruction sets, one of which is … Read more
Previously, we discussed how to run the RISC-V kernel on QEMU. Now, let’s talk about how to use Eclipse + GDB to debug the kernel on the QEMU platform. ${SIFIVE_DIR} is the local root directory of the freedom-u-sdk open-source project. 1. Configure BBL Configure the bootloader and generate debugging information. Enter the ${SIFIVE_DIR}/work/riscv-pk directory, which … Read more
Article Title: Cloud Task Scheduling System for RISC-V Heterogeneous Clusters Based on Kubernetes All Authors: Jiang Xiaobin, Xiong Yixiang, Zhang Heng, Hou Pengpeng, Wu Yanjun, Zhao Chen First Affiliation: Institute of Software, Chinese Academy of Sciences Publication Time: 2022, 31(9): 3–14 Abstract Summary With the widespread application and attention in the field of cloud computing, … Read more
Abstract: The RISC-V instruction set has formed a significant advantage over ARM and Intel due to its open-source sharing, and its application is gradually expanding globally, resulting in a large amount of research literature. This study uses important literature on RISC-V themes worldwide as a dataset and analyzes the research trends, main research institutions, and … Read more
RISC-V is also known as “the Linux of CPUs.” For some, this title feels like a legacy and an innovation at the same time, especially if you are a staunch believer in open source. However, I am a true pragmatist, and the excessive marketing of RISC-V has made me lose interest in the term. It … Read more
RISC-V is an instruction set architecture (ISA) for microprocessors, and people’s opinions about it are polarized. This is especially true given the apparent competition between the ARM and RISC-V camps. This makes sense. RISC-V and ARM represent fundamentally different philosophies on how to design RISC chips. RISC-V has a long-term view that emphasizes simplicity, avoiding … Read more
| Source: SIMIT Strategic Research Office (ID: SIMITSRO) Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences The two major architectures of current CPUs are CISC (Complex Instruction Set) and RISC (Reduced Instruction Set). x86 is the representative architecture of CISC, occupying over 95% of the desktop computer and server market. Arm, as … Read more