What are the differences between STM32F1 and F4?

Answer:

Refer to: STM32 Development – Introduction to STM32 Core Differences: F1 uses Cortex-M3 core, while F4 uses Cortex-M4 core; different clock frequencies: F1 operates at 72MHz, F4 at 168MHz; floating-point operations: F1 lacks a floating-point unit, while F4 has one; functional performance: F4 has richer peripherals and more powerful functionality compared to F1, such as GPIO toggle rate, pull-up/pull-down resistor configuration, ADC precision, etc.; memory size: F1 has a maximum internal SRAM of 64K, while F4 has 192K (112+64+16).

2. Describe the STM32 startup process?

Answer:

Refer to: STM32 Development – Startup Process through Boot pins settings, finding the initial address initializing the stack pointer __initial_sp pointing to the reset program Reset_Handler setting exception interrupts HardFault_Handler setting system clock SystemInit calling C library function _main

3. Describe GPIO?

Answer:

Refer to: STM32 Development – Detailed Explanation of GPIO 8 working modes (gpio_init.GPIO_Mode): (1) GPIO_Mode_AIN Analog Input (2) GPIO_Mode_IN_FLOATING Floating Input (3) GPIO_Mode_IPD Pull-Down Input (4) GPIO_Mode_IPU Pull-Up Input (5) GPIO_Mode_Out_OD Open-Drain Output (6) GPIO_Mode_Out_PP Push-Pull Output (7) GPIO_Mode_AF_OD Alternate Function Open-Drain Output (8) GPIO_Mode_AF_PP Alternate Function Push-Pull Output

APB2 is responsible for AD, I/O, advanced TIM, UART1. APB1 is responsible for DA, USB, SPI, I2C, CAN, UART2345, basic TIM, PWR

GPIO Block Diagram Analysis: Refer to the public accountArticle:Detailed Explanation of GPIO Working Principles in STM32

4. UART

• Question 1: Introduction to serial communication methods? Synchronous communication: I2C half-duplex, SPI full-duplex; Asynchronous communication: RS485 half-duplex, RS232 full-duplex

• Question 2: Serial port configuration? The general steps for serial port settings can be summarized as follows: (1) Enable serial port clock, enable GPIO clock (2) Reset serial port (3) Set GPIO port mode TX’s GPIO working mode: GPIO_Mode_AF_PP; // Alternate Function Push-Pull Output RX’s GPIO working mode: GPIO_Mode_IN_FLOATING; // Floating Input (4) Serial port parameter initialization mainly includes: baud rate settings (115200), 8 data bits, 1 stop bit, no parity bit, no hardware flow control, transmission mode. (5) Enable interrupts and initialize NVIC (if interrupt needs to be enabled, this step is necessary) (6) Enable serial port (7) Write interrupt handling function

• Question 3: Main features of USART? (1) Full-duplex operation (independent reception and transmission of data); (2) In synchronous operation, can synchronize with host clock or slave clock; (3) Independent high-precision baud rate generator, does not occupy timer/counter; (4) Supports 5, 6, 7, 8, and 9 data bits, 1 or 2 stop bits serial data frame structure; (5) Hardware-supported parity bit generation and checking; (6) Data overflow detection; (7) Frame error detection; (8) Includes error start bit detection noise filter and digital low-pass filter; (9) Three completely independent interrupts: TX transmission complete, TX data register empty, RX reception complete; (10) Supports multi-device communication mode; (11) Supports double-speed asynchronous communication mode.

Answer:

Refer to: STM32 Development – Detailed Explanation of Serial Ports Application Scenarios: GPS, Bluetooth, 4G Modules

5. I2C

• Question 1: What are the three types of signals during data transmission on the I2C bus? (1) Start signal: When SCL is high, SDA transitions from high to low, starting data transmission. (2) Stop signal: When SCL is high, SDA transitions from low to high, ending data transmission. (3) Acknowledge signal: The receiving IC sends a specific low pulse to the transmitting IC after receiving 8 bits of data, indicating that the data has been received. The CPU issues a signal to the controlled unit and waits for the controlled unit to send an acknowledgment signal. After receiving the acknowledgment signal, the CPU determines whether to continue transmitting signals based on the actual situation. If no acknowledgment signal is received, it indicates a fault in the controlled unit.

• Question 2: How to configure the I2C master mode port? Hardware mode: Alternate Function Open-Drain Output, neither pull-up nor pull-down. (Fast mode: 400 Kbit/s) Software simulation: Push-Pull Output, configure pull-up resistors.

• Question 3: I2C arbitration mechanism? Refer to: S5PV210 Development – How Much Do You Know About I2C? (3) I2C Arbitration Mechanism, once you understand the “wired-AND,” it becomes clear. Simply put, it follows the principle of “low level priority,” i.e., whoever sends a low level first will take control of the bus.

Answer:

Refer to: STM32 Development – Detailed Explanation of PMIC, I2C Hardware Mode: Communication rate settings are available

/* STM32 I2C Fast Mode */#define I2C_Speed 400000/* Communication rate */I2C_InitStructure.I2C_ClockSpeed = I2C_Speed;

Software simulation: If no communication rate is set, how to calculate it? Through the I2C bus bit delay function i2c_Delay:

static void i2c_Delay(void){  uint8_t i;  /* The following time is obtained through testing with the Anfu Lai AX-Pro logic analyzer. When the CPU clock frequency is 72MHz, running in internal Flash, MDK project not optimized, when the loop count is 10, SCL frequency = 205KHz when the loop count is 7, SCL frequency = 347KHz, SCL high level time 1.5us, SCL low level time 2.87us when the loop count is 5, SCL frequency = 421KHz, SCL high level time 1.25us, SCL low level time 2.375us IAR project's compile efficiency is high, cannot be set to 7 */  for (i = 0; i < 10; i++);}

Application scenarios: PMIC, accelerometer, gyroscope

6. SPI

• Question 1: How many wires does SPI need? The SPI interface generally uses 4 wires for communication: MISO master device data input, slave device data output. MOSI master device data output, slave device data input. SCLK clock signal, generated by the master device. CS chip select signal, controlled by the master device.

• Question 2: What are the four modes of SPI communication? SPI has four working modes, each differing in SCLK, specifically determined by CPOL and CPHA. (1) CPOL: (Clock Polarity), SPI’s CPOL indicates whether the level of SCLK is low (0) or high (1) when idle: CPOL=0 means SCLK is low when idle, so when SCLK is active, it is high (active-high); CPOL=1 means SCLK is high when idle, so when SCLK is active, it is low (active-low);

(2) CPHA: (Clock Phase), the phase corresponds to the data sampling on which edge (the first or second edge), 0 corresponds to the first edge, 1 corresponds to the second edge. For: CPHA=0, it indicates the first edge: for CPOL=0, when idle it is low, the first edge is from low to high, so it is the rising edge; for CPOL=1, when idle it is high, the first edge is from high to low, so it is the falling edge; CPHA=1 indicates the second edge: for CPOL=0, when idle it is low, the second edge is from high to low, so it is the falling edge; for CPOL=1, when idle it is high, the first edge is from low to high, so it is the rising edge;

• Question 3: How to determine which mode to use? (1) First confirm the SCLK polarity required by the slave, whether it is at low or high when idle, thus confirming CPOL is 0 or 1. From the schematic, we set the idle state of the serial synchronous clock to high, so we choose SPI_CPOL_High, meaning CPOL is 1 (2) Then confirm from the slave chip’s datasheet timing diagram whether the slave chip samples data on the falling or rising edge of SCLK. To translate: W25Q32JV is accessed via SPI-compatible bus, including four signals: serial clock (CLK), chip select (/CS), serial data input (DI), and serial data output (DO). Standard SPI commands use the DI input pin to serially write commands, addresses, or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. The SPI bus operates in modes 0 (0,0) and 3 (1,1). Modes 0 and 3 focus on the normal state of the CLK signal when the SPI bus master is idle, and no data is being transmitted to the serial Flash. For mode 0, the CLK signal is typically low on the falling and rising edges / CS. For mode 3, the CLK signal is typically high on the falling and rising edges of /CS. Since the idle state of the serial synchronous clock is high, we choose the second transition edge, thus selecting SPI_CPHA_2Edge, meaning CPHA is 1, thus we choose mode 3 (1,1).

Answer:

Refer to: STM32 Development – Detailed Explanation of W25Q32JV SPI Flash Refer to: Detailed Explanation of CPOL and CPHA in SPI Application Scenarios: SPI Flash, W25Q32 Memory Capacity 32Mb (4M x 8), which is 4M byte

7. CAN

• Question 1: Briefly introduce CAN? The CAN controller determines the bus level based on the voltage difference on CAN_L and CAN_H. The bus level is divided into dominant and recessive levels, one of which is taken. The sender sends the message to the receiver by changing the bus level.

• Question 2: What are the steps for CAN initialization configuration? (1) Configure the multiplexing function of related pins, enable CAN clock (2) Set CAN operating mode and baud rate, etc. (CAN initialization loopback mode, baud rate 500Kbps) (3) Set the filter

• Question 3: CAN data sending format? CanTxMsg TxMessage; TxMessage.StdId=0x12; // Standard Identifier TxMessage.ExtId=0x12; // Set Extended Identifier TxMessage.IDE=CAN_Id_Standard; // Standard Frame TxMessage.RTR=CAN_RTR_Data; // Data Frame TxMessage.DLC=len; // Length of data to be sent Send 8 bytes for(i=0;i<len;i++) TxMessage.Data[i]=msg[i]; // Data

Answer:

Refer to: STM32 Development – Detailed Explanation of CAN Bus

8. DMA

• Question 1: What is DMA? Direct Memory Access (DMA) is used to provide high-speed data transfer between peripherals and memory or between memory and memory. Data can be moved quickly through DMA without CPU intervention, saving CPU resources for other operations.

• Question 2: How many DMA transfer modes are there? DMA_Mode_Circular Circular Mode DMA_Mode_Normal Normal Buffer Mode Application Scenarios: GPS, Bluetooth, both use Circular Collection, DMA_Mode_Circular mode.

Answer:

Refer to the article: Detailed Explanation of DMA Principles in STM32

A relatively important function is to obtain the current remaining data size, which is the size of the reception buffer set minus the current remaining data size, yielding the current amount of received data.

9. Interrupts

• Question 1: Describe the interrupt handling process? (1) Initialize the interrupt, set the trigger method to rising edge/falling edge/both edges. (2) Trigger the interrupt, enter the interrupt service function

• Question 2: How many external interrupts does the STM32 interrupt controller support? The STM32 interrupt controller supports 19 external interrupts/event requests: From the diagram, GPIO pins GPIOx.0~GPIOx.15 (x=A, B, C, D, E, F, G) correspond to interrupt lines 0 ~ 15. The other four EXTI lines are connected as follows: ● EXTI line 16 connects to PVD output ● EXTI line 17 connects to RTC alarm event ● EXTI line 18 connects to USB wakeup event ● EXTI line 19 connects to Ethernet wakeup event (only applicable to interconnect products) The interrupt service function list: The external interrupt on IO ports only allocates 7 interrupt vectors in the interrupt vector table, meaning only 7 interrupt service functions can be used. EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler EXTI9_5_IRQHandler EXTI15_10_IRQHandler

Answer:

Refer to: STM32 Development – Detailed Explanation of External Interrupts

10. How many clock sources does STM32 have?STM32 has 5 clock sources: HSI, HSE, LSI, LSE, PLL. ① HSI is the high-speed internal clock, RC oscillator, frequency is 8MHz, accuracy is not high. ② HSE is the high-speed external clock, which can connect quartz/ceramic resonators or external clock sources, with a frequency range of 4MHz~16MHz. ③ LSI is the low-speed internal clock, RC oscillator, frequency is 40kHz, providing low-power clock. ④ LSE is the low-speed external clock, connected to a quartz crystal with a frequency of 32.768kHz. ⑤ PLL is a phase-locked loop frequency multiplier output, whose clock input source can be selected as HSI/2, HSE, or HSE/2. The multiplication factor can be chosen from 2 to 16 times, but its output frequency must not exceed 72MHz.

Answer:

Refer to the article: Detailed Explanation of STM32 Clock System, saved

11. How to write tasks in RTOS? How to switch out this task?

Answer:

A task, also known as a thread. UCOS has a task scheduling mechanism that schedules based on task priority. One is hardware interrupts, so the system will push the current task-related variables onto the stack, then execute the interrupt service routine, and pop the stack after the execution is complete. The other is task switching, done through task scheduling, where each task has its own stack, and similarly, it is pushed onto the stack, then executes another program, and pops out to return.

Not every task executes in strict priority order; rather, high-priority tasks run exclusively, and unless they voluntarily yield execution, low-priority tasks cannot preempt them. At the same time, high-priority tasks can reclaim CPU usage that was yielded to low-priority tasks. Therefore, in UCOS, it is important to insert wait delays between tasks to allow UCOS to switch out and let lower-priority tasks execute.

12. What are the communication methods between tasks in UCOSII?

Answer:

In UCOSII, communication between tasks is achieved using semaphores, mailboxes (message mailboxes), and message queues, which are referred to as events, as well as global variables. Semaphore: Refer to: Summary of UCOSII Semaphore Usage (Example Explanation) Semaphores are used for: 1. Controlling the use of shared resources (satisfying mutual exclusion conditions) 2. Indicating the occurrence of a certain time 3. Synchronizing the behavior of two tasks

Application example: A mutex semaphore as a mutual exclusion condition, initialized to 1. The goal is to call the serial port to send a command, which must wait for the return of the “OK” character before sending the next command. Each task may use this sending function, and conflicts must be avoided!

Mailbox (message mailbox):

Message Queue: Concept: (1) A message queue is essentially an array of mailboxes. (2) Both tasks and interrupts can place a message into the queue, and tasks can retrieve messages from the message queue. (3) The first message to enter the queue is the first to be passed to the task (FIFO). (4) Each message queue has a waiting list of tasks waiting for messages; if there are no messages in the queue, the waiting tasks are suspended until a message arrives.

Application scenario: The receive buffer in the serial receiving program. Storing external events.

13. The project uses a custom protocol, what is its structure?

Answer:

Familiar with the Modbus protocol. The structure is: Frame Header (SDTC) + Frame Length + Command + Serial Number + Data + CRC Check.

14. What are the differences between uCOSII and Linux?

Answer:

μC/OS-II is specifically designed for embedded applications in computers. μC/OS-II features high execution efficiency, small footprint, excellent real-time performance, and strong scalability, with the minimum kernel compiled to 2KB. μC/OS-II has been ported to nearly all well-known CPUs. Linux is free, secure, stable, and widely used across various applications, including embedded systems, servers, and personal computers. Both μC/OS-II and Linux are suitable for embedded use. However, μC/OS-II is designed specifically for embedded systems, resulting in higher operational efficiency and lower resource usage. Linux can be used as a server, with high usage rates. Although Linux was not specifically developed for servers, its open-source nature allows for modifications, making the differences between the two not significant, with the main distribution, Red Hat Linux, being widely used in server systems.

15. Git commit process

Question: What is the Git commit process?

Answer:

1. Display modified files in the working path:

$ git status

2. Enter the modified file directory:

$cd -

3. Display differences from the last commit version:

$ git diff

4. Add all current modifications to the next commit:

$ git add .

5. Add relevant functional descriptions (use this for the first commit)

$ git commit -s

Where you also need to specify: Function: Description of the modified functionality Ticket: Corresponding bug number Note: Each folder must be submitted again. 6. View submitted code

$ tig .

7. Do not modify already published commit records! (Use this for future submissions)

$git commit --amend

In command mode: 😡 (write file and exit) 8. Push to the server

$ git push origin HEAD:refs/for/master

16. Comparison of ucosii, ucosiii, and freeRTOS

• Question 1: Comparison of the three?

Answer:

Comparison between ucosii and freeRTOS: (1) FreeRTOS only supports TCP/IP, while uCOSii has extensive external support, such as FS, USB, GUI, CAN, etc. (We chose uCOSii for the tbox due to CAN requirements.) (2) FreeRTOS is free for commercial use. uCOSii requires payment for commercial use. (3) FreeRTOS only supports queues, semaphores, and mutexes for inter-task communication. In addition to these, uCOSii also supports event flag groups and mailboxes. (4) Theoretically, freeRTOS can manage more than 64 tasks, while uCOSii can only manage 64.

Comparison between ucosii and ucosiii: What are the differences from μC/OS-II to μC/OS-III? There have been significant changes. One is that originally only 0~63 priority levels were allowed, and priorities could not be duplicated; now several tasks can use the same priority, and time-slicing scheduling is supported within the same priority. Secondly, users can dynamically configure real-time operating system kernel resources during program execution, such as tasks, task stacks, semaphores, event flag groups, message queues, message counts, mutex semaphores, memory block divisions, and timers, which can be changed during program execution. This allows users to avoid resource allocation problems during program compilation. Improvements have also been made in resource reuse. In μC/OS-II, the maximum number of tasks is 64; after version 2.82, it increased to 256. In μC/OS-III, users can have any number of tasks, semaphores, mutex semaphores, event flags, message lists, timers, and any allocated memory block capacity, limited only by the amount of RAM available to the user’s CPU. This is also a significant expansion. (Question: Teacher Shao, is this number fixed at startup or can it be freely defined after startup?) It can be freely defined during configuration, as long as your RAM is sufficient. The fourth point is that many functions have been added, and the number of functions is always increasing; everyone can take a look. Originally, these functions were not available in μC/OS-II.

17. Low Power Modes

• Question 1: What are the types of low power modes? What are the wake-up methods?

Answer:

18. IoT Architecture

• Question 1: How many layers are there in IoT architecture? What functions does each layer perform?

Answer:

Divided into three layers, IoT can be structurally divided into a perception layer, network layer, and application layer. (1) Perception layer: Responsible for information collection and information transmission between objects. Information collection technologies include sensors, barcodes and QR codes, RFID technology, audio and video multimedia information, and information transmission includes near and far distance data transmission technologies, self-organizing networking technologies, collaborative information processing technologies, and information collection middleware technologies in sensor networks. The perception layer is the core capability for achieving comprehensive perception in the IoT and is the part that urgently needs breakthroughs in key technologies, standardization, and industrialization, with the key being to possess more accurate and comprehensive perception capabilities while solving problems of low power consumption, miniaturization, and low cost. (2) Network layer: Utilizes wireless and wired networks to encode, authenticate, and transmit collected data. The widely covered mobile communication network serves as the infrastructure for realizing IoT, being the most standardized, industrialized, and mature part of the three layers of IoT, with the key being to optimize and improve the application characteristics of IoT to form a network of collaborative perception. (3) Application layer: Provides rich IoT-based applications, which is the fundamental goal of IoT development, combining IoT technology with industry information needs to achieve a wide range of intelligent application solutions, with the key being industry integration, development and utilization of information resources, low-cost high-quality solutions, ensuring information security, and developing effective business models.

19. Memory Management

• Question 1: What methods are there for memory management in UCOS?

Answer:

The system manages memory partitions through memory control blocks associated with memory partitions.

Dynamic memory management functions include: Create dynamic memory partition function OSMemCreate(); Request to obtain memory block function OSMemGet(); Release memory block function OSMemPut();

20. What are the task states in Ucos? What is the relationship diagram between task states?

Answer:

There are 5 states: Sleep state, Ready state, Running state, Waiting state (waiting for a specific event to occur), and Interrupt Service state.

The 5 state transition relationships of UCOSII tasks:

21. ADC

• Question 1: Briefly describe the functional characteristics of the STM32 ADC system? (1) 12-bit resolution (2) Automatic calibration (3) Programmable data alignment (conversion results can be stored in 16-bit data registers in either left or right aligned format) (4) Single and continuous conversion modes

Answer:

Refer to the article: Detailed Explanation of ADC in STM32

22. System Clock

• Question 1: Briefly describe the basic process for setting the system clock? (1) Turn on HSE, wait until ready, then set Flash wait operations. (2) Set AHB, APB1, APB2 division factors, determining their respective relationships with the system clock. (3) Set CFGR register to determine the clock source and multiplication factor for PLL (HSE external 8M * 9 times = 72MHz). (4) Enable PLL, switch the system clock source to PLL.

Answer:

23. Handling of HardFault_Handler

• Question 1: What are the causes? (1) Array out of bounds operation; (2) Memory overflow, out-of-bounds access; (3) Stack overflow, program runaway; (4) Interrupt handling errors;

• Question 2: What are the handling methods? (1) In startup_stm32f10x_cl.s find the address remapping of HardFault_Handler and rewrite it to jump to the HardFaultHandle function. (2) Print and check the registers R0, R1, R2, R3, R12, LR, PC, PSR. (3) Check the Fault status register group (SCB->CFSR and SCB->HFSR)

24. TTS Speech Synthesis Method

• Question 1: What method does sim7600 TTS speech use?

Answer:

(1) Uses unicode encoding to synthesize sound AT+CTTS=1,”6B228FCE4F7F75288BED97F3540862107CFB7EDF” content is “Welcome to the speech synthesis system,” the module sends and receives Chinese text messages using unicode encoding, making it easy to read messages aloud; (2) Directly input text, ordinary characters use ASCII code, Chinese characters use GBK encoding. AT+CTTS=2,”Welcome to the speech synthesis system”

25. Timer

• Question 1: Given that the STM32 system clock is 72MHz, how to set related registers to achieve a 20ms timer?

Answer:

Refer to the article: STM32 Beginner Series – SysTick System TimerThrough SysTick_Config(SystemCoreClock / OS_TICKS_PER_SEC))//1ms timerWhere:

uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */#define SYSCLK_FREQ_72MHz  72000000#define OS_TICKS_PER_SEC       1000    /* Set the number of ticks in one second

If 20ms is needed, you can set a global variable and initialize it to 20, so that each SysTick interrupts once, this global variable decreases by 1, until it reaches 0, which means the SysTick has interrupted 20 times, and the time is: 1ms * 20 = 20ms. Thus, achieving a 20ms timer.

26. Priority

• Question 1: How do two tasks with the same priority run?

Answer:

Make the priority of the task obtaining the semaphore temporarily elevated to one level above the highest priority of all tasks during the use of shared resources, so that this task is not interrupted by other tasks, allowing it to quickly finish using the shared resources and releasing the semaphore, then restore the original priority of that task after releasing the semaphore.

27. State Machine

• Question 1: What state machine is used?

Answer:

Refer to the article: Discussing the Programming Philosophy of Microcontrollers – State Machine

Finite State Machine (FSM), also known as a finite state automaton, abbreviated as state machine.

Assuming the state transitions of the state machine are shown in the table below:

Implementation: (using switch statement)

// Written horizontallyvoid event0func(void){    switch(cur_state)    {        case State0:             action0;             cur_state = State1;        break;         case State1:             action1;             cur_state = State2;        break;         case State2:             action1;             cur_state = State0;        break;        default:break;    }} void event1func(void){    switch(cur_state)    {        case State0:             action4;             cur_state = State1;        break;        default:break;    }} void event2func(void){    switch(cur_state)    {        case State0:             action5;             cur_state = State2;        break;         case State1:             action6;             cur_state = State0;        break;        default:break;    }}

28. Device Selection

• Question 1: Comparison of STM32F407 vs STM32F103 main functions and resources?

Answer:

Source: juyou.blog.csdn.net/article/details/116021595