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Answer:
Reference: STM32 Development – Introduction to STM32Different Kernels: F1 uses Cortex-M3, F4 uses Cortex-M4; Different Clock Frequencies: F1 operates at 72MHz, F4 at 168MHz; Floating Point Operations: F1 lacks a floating point unit, while F4 has one; Functional Performance: F4 has more peripherals with stronger functions than F1, such as GPIO toggle rate, pull-up/pull-down resistor configuration, ADC precision, etc.; Memory Size: F1 has a maximum of 64K internal SRAM, while F4 has 192K (112+64+16).
2. Describe the STM32 startup process?
Reference: STM32 Development – Startup ProcessSet by Boot pins, find the initial address to initialize stack pointer __initial_sp pointing to the reset program Reset_Handler, set the exception interrupt HardFault_Handler, set system clock SystemInit, call C library function _main
Reference: STM32 Development – Detailed GPIO Explanation
8 GPIO Operating Modes (gpio_init.GPIO_Mode):(1) GPIO_Mode_AIN Analog Input (2) GPIO_Mode_IN_FLOATING Floating Input (3) GPIO_Mode_IPD Pull-Down Input (4) GPIO_Mode_IPU Pull-Up Input (5) GPIO_Mode_Out_OD Open-Drain Output (6) GPIO_Mode_Out_PP Push-Pull Output (7) GPIO_Mode_AF_OD Alternate Function Open-Drain Output (8) GPIO_Mode_AF_PP Alternate Function Push-Pull Output
APB2 is responsible for AD, I/O, advanced TIM, and Serial Port 1.APB1 is responsible for DA, USB, SPI, I2C, CAN, Serial Ports 2345, General TIM, PWR
GPIO Block Diagram Analysis: Reference: STM32-GPIO Detailed Explanation
Question 1: Introduction to Serial Communication Methods? Synchronous Communication: I2C Half-Duplex, SPI Full-Duplex Asynchronous Communication: RS485 Half-Duplex, RS232 Full-Duplex
Question 2: Serial Port Configuration? The general steps for serial port settings can be summarized as follows: (1) Enable Serial Port Clock, Enable GPIO Clock (2) Reset Serial Port (3) Set GPIO Port Mode TX GPIO working mode: GPIO_Mode_AF_PP; // Alternate Function Push-Pull Output RX GPIO working mode: GPIO_Mode_IN_FLOATING; // Floating Input (4) Serial Port Parameter Initialization mainly includes: Baud Rate Setting (115200), 8 Data Bits, 1 Stop Bit, No Parity Bit, No Hardware Flow Control, Transmit and Receive Mode. (5) Enable Interrupts and Initialize NVIC (if interrupts need to be enabled, this step is necessary) (6) Enable the Serial Port (7) Write Interrupt Handler Function
Question 3: Main Features of USART? (1) Full-Duplex Operation (independent reception and transmission of data); (2) In synchronous operation, can synchronize with master or slave clock; (3) Independent high-precision baud rate generator, does not occupy timer/counter; (4) Supports 5, 6, 7, 8, and 9 data bits, and 1 or 2 stop bits for serial data frame structure; (5) Hardware-supported parity bit generation and checking; (6) Data overflow detection; (7) Frame error detection; (8) Includes error start bit detection noise filter and digital low-pass filter; (9) Three completely independent interrupts, TX transmission complete, TX data register empty, RX reception complete; (10) Supports multi-master communication mode; (11) Supports double-speed asynchronous communication mode.
Reference: STM32 Development – Detailed Serial Port Explanation Application Scenarios: GPS, Bluetooth, 4G Modules
Question 1: What are the three types of signals during data transmission on the I2C bus? (1) Start Signal: When SCL is high, SDA transitions from high to low to start data transmission. (2) Stop Signal: When SCL is high, SDA transitions from low to high to end data transmission. (3) Acknowledge Signal: The IC receiving data sends a specific low pulse to the transmitting IC after receiving 8 bits of data, indicating that the data has been received. The CPU sends a signal to the controlled unit and waits for the controlled unit to send an acknowledgment signal. After receiving the acknowledgment signal, the CPU decides whether to continue transmitting signals based on the actual situation. If no acknowledgment signal is received, it is judged that the controlled unit has failed.
Question 2: How to configure the I2C master mode port? Hardware Mode: Alternate Function Open-Drain Output, neither pull-up nor pull-down. (Fast Mode: 400 Kbit/s) Software Simulation: Push-Pull Output, configure pull-up resistor.
Question 3: I2C Arbitration Mechanism? Reference: S5PV210 Development – How Much Do You Know About I2C? (3) I2C arbitration mechanism is clear once you understand the line “AND” (Wired-AND). In simple terms, it follows the principle of “low level first”, meaning whoever sends a low level first will gain control of the bus.
Reference: STM32 Development – PMIC, I2C Detailed Explanation Hardware Mode: has communication rate settings /* STM32 I2C Fast Mode */#define I2C_Speed 400000
/* Communication Rate */I2C_InitStructure.I2C_ClockSpeed = I2C_Speed;
Software Simulation: If no communication rate is set, how to calculate it? By using the I2C bus bit delay function i2c_Delay:
static void i2c_Delay(void)
{
uint8_t i;
/*
The following times are obtained through testing with the Anfu Lai AX-Pro logic analyzer.
When CPU frequency is 72MHz, running in internal Flash, MDK project not optimized
When loop count is 10, SCL frequency = 205KHz
When loop count is 7, SCL frequency = 347KHz, SCL high time 1.5us, SCL low time 2.87us
When loop count is 5, SCL frequency = 421KHz, SCL high time 1.25us, SCL low time 2.375us
IAR project has higher compilation efficiency, cannot set to 7
*/
for (i = 0; i < 10; i++);
}
Application Scenarios: PMIC, Accelerometer, Gyroscope
Question 1: How many lines does SPI need? The SPI interface generally uses 4 lines for communication: MISO master device data input, slave device data output. MOSI master device data output, slave device data input. SCLK clock signal generated by the master device. CS chip select signal controlled by the master device.
Question 2: What are the four modes of SPI communication? SPI has four working modes, each differing in SCLK, specifically determined by CPOL and CPHA. (1) CPOL: (Clock Polarity), clock polarity: SPI’s CPOL indicates whether the level of SCLK is low (0) or high (1) when idle: CPOL=0 means the clock is low when idle, so when SCLK is active, it is high, known as active-high; CPOL=1 means the clock is high when idle, so when SCLK is active, it is low, known as active-low;
(2) CPHA:(Clock Phase), clock phase: Phase corresponds to data sampling at which edge (first or second edge), 0 corresponds to the first edge, and 1 corresponds to the second edge. For: CPHA=0, the first edge corresponds to the low-to-high transition; for CPOL=0, when idle, it is low, so the first edge is the rising edge; for CPOL=1, when idle, it is high, so the first edge is the falling edge; CPHA=1 indicates the second edge: for CPOL=0, when idle, it is low, so the second edge is the falling edge; for CPOL=1, when idle, it is high, so the first edge is the rising edge;
Question 3: How to determine which mode to use? (1) First confirm the SCLK polarity required by the slave; when not working, whether it is at low or high potential, thus confirming CPOL as 0 or 1. Looking at the schematic, we set the idle state of the serial synchronous clock as high, so we choose SPI_CPOL_High. That is, CPOL is 1 (2) Then confirm from the slave chip’s datasheet whether the slave chip samples data on the falling or rising edge of SCLK. Translation: W25Q32JV accesses via SPI-compatible bus, including four signals: serial clock (CLK), chip select (/CS), serial data input (DI), and serial data output (DO). Standard SPI commands use the DI input pin to serially write commands, addresses, or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. Supports mode 0 (0,0) and 3 (1,1) SPI bus operation. Modes 0 and 3 focus on the normal state of the CLK signal when the SPI bus master is idle and no data is being transmitted to serial Flash. For mode 0, the CLK signal is usually low on the falling and rising edges/ CS. For mode 3, the CLK signal is usually high on the falling and rising edges of /CS. Since the idle state of the serial synchronous clock is high, we choose the second transition edge, thus selecting SPI_CPHA_2Edge. That is, CPHA is 1 so we choose mode 3 (1,1).
Reference: STM32 Development – W25Q32JV SPI Flash Detailed Explanation Reference: Detailed Explanation of CPOL and CPHA in SPI Application Scenarios: SPI Flash, W25Q32 Memory Capacity 32Mb (4M x 8), that is 4M byte
Question 1: Briefly summarize CAN? The CAN controller determines the bus level based on the potential difference on CAN_L and CAN_H. The bus level is divided into dominant and recessive levels, and one of them is chosen. The sender sends the message to the receiver by changing the bus level.
Question 2: Steps for CAN initialization configuration? (1) Configure the multiplexing function of related pins, enable CAN clock (2) Set CAN working mode and baud rate, etc. (Initialize CAN in loopback mode, baud rate 500Kbps) (3) Set filters
Question 3: CAN data sending format? CanTxMsg TxMessage; TxMessage.StdId=0x12; // Standard Identifier TxMessage.ExtId=0x12; // Set Extended Identifier TxMessage.IDE=CAN_Id_Standard; // Standard Frame TxMessage.RTR=CAN_RTR_Data; // Data Frame TxMessage.DLC=len; // Length of data to be sent 8 bytes for(i=0;i<len;i++) TxMessage.Data[i]=msg[i]; // data
Reference: STM32 Development – Detailed Explanation of CAN Bus
Question 1: What is DMA? Direct Memory Access (DMA) is used to provide high-speed data transfer between peripherals and memory or between memory and memory. Data can move quickly through DMA without CPU intervention, saving CPU resources for other operations.
Question 2: What types of DMA transfer modes are there? DMA_Mode_Circular Circular Mode DMA_Mode_Normal Normal Buffer Mode Application Scenarios: GPS, Bluetooth, both use circular sampling, DMA_Mode_Circular mode.
Reference: STM32 Development – Detailed Explanation of DMA
A relatively important function retrieves the current remaining data size, based on the configured receive buffer size minus the current remaining data size, to get the current received data size.
Question 1: Describe the interrupt handling process? (1) Initialize the interrupt, set the trigger mode to rising edge/falling edge/both edges. (2) Trigger the interrupt, enter the interrupt service function
Question 2: How many external interrupts does STM32’s interrupt controller support? STM32’s interrupt controller supports 19 external interrupt/event requests: From the diagram, GPIO pins GPIOx.0~GPIOx.15 (x=A, B, C, D, E, F, G) correspond to interrupt lines 0 ~ 15. The connection methods for the other four EXTI lines are as follows: ● EXTI line 16 connected to PVD output ● EXTI line 17 connected to RTC alarm event ● EXTI line 18 connected to USB wake-up event ● EXTI line 19 connected to Ethernet wake-up event (only applicable to Internet products) The interrupt service function list: External interrupt on IO ports only allocates 7 interrupt vectors in the interrupt vector table, meaning only 7 interrupt service functions can be used. EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler EXTI9_5_IRQHandler EXTI15_10_IRQHandler
Reference: STM32 Development – Detailed Explanation of External Interrupts
10. How many clock sources does STM32 have?
STM32 has 5 clock sources: HSI, HSE, LSI, LSE, PLL. ① HSI is a high-speed internal clock, RC oscillator, frequency is 8MHz, with low accuracy. ② HSE is a high-speed external clock, can connect quartz/ceramic resonators or external clock sources, frequency range is 4MHz~16MHz. ③ LSI is a low-speed internal clock, RC oscillator, frequency is 40kHz, providing low-power clock. ④ LSE is a low-speed external clock, connected to a quartz crystal with a frequency of 32.768kHz. ⑤ PLL is a phase-locked loop frequency multiplier output, whose clock input source can be selected as HSI/2, HSE, or HSE/2. The frequency multiplier can be selected from 2 to 16 times, but its output frequency must not exceed 72MHz.
Reference: STM32 Development – Detailed Explanation of Clock System
11. How to write tasks in RTOS? How to switch out this task?
A task, also known as a thread.
UCOS has a task scheduling mechanism, scheduled according to task priority.
One is hardware interrupt, the system will push the related variables of the current task onto the stack, then execute the interrupt service program, and pop the stack to return after execution.
The other is the switching between tasks, the method used is task scheduling, each task has its own stack, the same is pushed onto the stack, then executes another program, then pops back.
Not every task executes in order of priority; rather, high-priority tasks run exclusively unless they voluntarily yield execution, otherwise low-priority tasks cannot preempt them. At the same time, high-priority tasks can reclaim CPU occupancy that was given to low-priority tasks. Therefore in UCOS, it is important to insert wait delays between tasks to allow UCOS to switch out to let lower-priority tasks execute.
12. What are the communication methods between tasks in UCOSII?
In UCOSII, semaphores, mailboxes (message mailboxes), and message queues are used as intermediate links called events to achieve communication between tasks, as well as global variables.
Semaphore: Reference: Summary of Semaphore Usage in ucosII (Example Explanation) Semaphores are used for: 1. Controlling the use of shared resources (satisfying mutual exclusion conditions) 2. Signaling the occurrence of an event 3. Synchronizing the behavior of two tasks
Application Example: Mutual semaphore as a mutual exclusion condition, initialized to 1. Implementation goal: Calling the serial port to send a command must wait for the return of the “OK” character before sending the next command. Each task may use this sending function, and conflicts must not occur!
Mailbox (message mailbox):
Message Queue: Concept: (1) A message queue is essentially an array of mailboxes. (2) Both tasks and interrupts can place a message into the queue, and tasks can retrieve messages from the message queue. (3) The first message to enter the queue is the first to be sent to the task (FIFO). (4) Each message queue has a waiting list of tasks waiting for messages; if there are no messages in the queue, the waiting tasks are suspended until a message arrives.
Application Scenario: Receiving buffer in serial port receiving program. Storing external events.
13. The project uses a custom protocol; what is its structure?
Familiar with the Modbus protocol. Structure: Frame Header (SDTC) + Frame Length + Command + Serial Number + Data + CRC Check.
14. Differences between uCOSII and Linux?
μC/OS-II is specifically designed for embedded applications, μC/OS-II has characteristics of high execution efficiency, small footprint, excellent real-time performance, and strong scalability, with a minimum kernel that can be compiled to 2KB. μC/OS-II has been ported to almost all well-known CPUs.
Linux is free, secure, stable, and widely applicable, used in embedded systems, servers, and personal computers.
Both μC/OS-II and Linux are suitable for embedded use. However, μC/OS-II is specifically designed for embedded systems, resulting in higher running efficiency and less resource usage.
Linux can be used as a server, with high usage. Although Linux is not specifically developed for servers, its source code is open, allowing for modifications, making the differences between the two not significant; the main distribution, Red Hat Linux, is widely used on servers.
Question: Process of Git committing code?
1. Display modified files in the working path:
$ git status
2. Enter the directory of modified files:
$cd -
3. Display differences from the last commit version:
$ git diff
4. Add all current modifications to the next commit:
$ git add .
5. Add relevant function description (use this for the first commit)
$ git commit -s
In addition, specify: Function: modification function Ticket: corresponding Bug number Note: Each folder must be submitted again. 6. View submitted code
$ tig .
7. Do not modify published commit records! (Use this for future submissions)
$git commit --amend
In command mode: 😡 (write file and exit) 8. Push to the server
$ git push origin HEAD:refs/for/master
16. Comparison of ucosii, ucosiii, and freeRTOS
Question 1: Comparison of the three?
Comparison of ucosii and freeRTOS:(1) freeRTOS supports only TCP/IP, while uCOSii has extensive external support, such as FS, USB, GUI, CAN, etc. (We need to use CAN for the tbox, so we chose uCOSii) (2) freeRTOS is commercially free to use. uCOSii requires payment for commercial use. (3) Communication between tasks: freeRTOS supports only queues, semaphores, and mutexes. uCOSii supports these plus event flag groups and mailboxes. (4) Theoretically, freeRTOS can manage more than 64 tasks, while uCOSii can only manage 64.
Comparison of ucosii and ucosiii: So what changes from μC/OS-II to μC/OS-III? A lot has changed. One is that it originally had only 0-63 priorities, and priorities could not be repeated, but now it allows multiple tasks to use the same priority, supporting time-slice scheduling within the same priority; the second is that it allows users to dynamically configure real-time operating system kernel resources during program execution, such as tasks, task stacks, semaphores, event flag groups, message queues, message counts, mutex semaphores, memory block divisions, and timers, which can be changed during program execution. This helps users avoid resource allocation issues during program compilation. Improvements have also been made in resource reuse. In μC/OS-II, the maximum number of tasks was 64; after version 2.82, it became 256, and in μC/OS-III, users can have any number of tasks, semaphores, mutex semaphores, event flags, message lists, timers, and memory blocks, limited only by the RAM available on the user’s CPU. This is a significant expansion. (Question: Teacher Shao, is this number fixed at startup or can it be set freely after startup?) It can be freely defined during configuration, as long as your RAM is large enough. The fourth point is that many functions have been added; the functionalities are always increasing, which you can check out. Originally, these functionalities were not available in μC/OS-II.
Question 1: What are the low power modes? What are the wake-up methods?
Answer:
Question 1: How many layers does the IoT architecture have? What functions does each layer perform? Answer:
Divided into three layers, the IoT architecture can be divided into perception layer, network layer, and application layer, (1) Perception Layer: Responsible for information collection and information transmission between objects; information collection technologies include sensors, barcodes and QR codes, RFID technology, audio and video, and other multimedia information; information transmission includes near and far distance data transmission technologies, self-organizing networking technologies, collaborative information processing technologies, middleware technologies for information collection, etc. The perception layer is the core capability for comprehensive perception in IoT, a crucial part where key technologies, standardization, and industrialization need breakthroughs, focusing on more precise and comprehensive perception capabilities while addressing low power consumption, miniaturization, and low-cost issues. (2) Network Layer: Utilizes wireless and wired networks to encode, authenticate, and transmit collected data; a widely covered mobile communication network is the infrastructure for realizing IoT, the most standardized, industrialized, and mature part of the three layers, focusing on optimizing and improving the characteristics of IoT applications, forming a collaborative perception network. (3) Application Layer: Provides rich IoT-based applications, which are the fundamental goal of IoT development, combining IoT technology with industry information needs to realize a wide range of intelligent application solutions, focusing on industry integration, development and utilization of information resources, low-cost high-quality solutions, ensuring information security, and developing effective business models.
Question 1: What methods are there for memory management in UCOS?
The system manages memory partitions through memory control blocks associated with memory partitions.
Dynamic memory management functions include: function to create dynamic memory partitions OSMemCreate(); function to request memory blocks OSMemGet(); function to release memory blocks OSMemPut();
20. What states do tasks have in Ucos? Draw the relationship diagram between task states?
There are 5 states: sleep state, ready state, running state, waiting state (waiting for a certain event to occur), and interrupt service state.
UCOSII task state transition relationships:
Question 1: Briefly describe the features of the STM32 ADC system? (1) 12-bit resolution (2) Automatic calibration (3) Programmable data alignment (conversion results support left or right alignment stored in 16-bit data register) (4) Single and continuous conversion modes
Reference: STM32 Development – Detailed Explanation of ADC
Question 1: Briefly describe the basic process of setting the system clock? (1) Enable HSE, wait for it to be ready, and set Flash wait operations. (2) Set the AHB, APB1, APB2 division coefficients, determining their relationship with the system clock. (3) Set the CFGR register to determine PLL’s clock source and multiplication factor (HSE external 8M * 9 times = 72MHz). (4) Enable PLL, switch the system clock source to PLL.
23. HardFault_Handler Handling
Question 1: What causes it?(1) Array out-of-bounds operation; (2) Memory overflow, out-of-bounds access; (3) Stack overflow, program runaway; (4) Interrupt handling errors;
Question 2: What are the handling methods? (1) Find the address remapping of HardFault_Handler in startup_stm32f10x_cl.s and rewrite it, to jump to the HardFaultHandle function.(2) Print and check registers R0, R1, R2, R3, R12, LR, PC, PSR. (3) Check the Fault status register group (SCB->CFSR and SCB->HFSR)
Reference: STM32 Development – HardFault_Handler Handling Reference: Cortex-M3 and Cortex-M4 Fault Exception Application One – Basic Knowledge
24. TTS Speech Synthesis Method
Question 1: What method does sim7600 TTS speech use?
(1) Use unicode encoding to synthesize sound AT+CTTS=1,”6B228FCE4F7F75288BED97F3540862107CFB7EDF” content is “Welcome to use the speech synthesis system”, the module sends and receives Chinese text messages in unicode encoding, so it is easy to read the messages aloud; (2) Directly input text, ordinary characters use ASCII code, Chinese characters use GBK encoding. AT+CTTS=2,”Welcome to use the speech synthesis system”
Question 1: Given that the STM32 system clock is 72MHz, how to set the relevant registers to achieve a 20ms timer?
Reference: STM32 Development – Systick Timer By SysTick_Config(SystemCoreClock / OS_TICKS_PER_SEC)) // 1ms timer
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
#define SYSCLK_FREQ_72MHz 72000000
#define OS_TICKS_PER_SEC 1000 /* Set the number of ticks in one second
If you need 20ms, you can set a global variable and initialize it to 20, so that every time the systick interrupts, this global variable decrements by 1, until it reaches 0, which means the systick interrupts 20 times, giving a time of: 1ms*20=20ms. Thus achieving a 20ms timer.
Question 1: How do two tasks with the same priority run?
Make the priority of the task obtaining the semaphore temporarily elevated to one level higher than the highest priority of all tasks during the use of shared resources, so that this task is not interrupted by other tasks, allowing it to quickly use the shared resources and release the semaphore, then after releasing the semaphore, restore the original priority of that task.
Question 1: What state machine is used?
Reference: STM32 Development – State Machine and State Transition Logic
Finite State Machine (FSM), also known as a finite state automaton. Reference: Detailed Explanation of Finite State Machine FSM and Its Implementation
Assuming the state transitions of the state machine are shown in the table below:
Implementation: (using switch statement)
// Written horizontally
void event0func(void)
{
switch(cur_state)
{
case State0:
action0;
cur_state = State1;
break;
case State1:
action1;
cur_state = State2;
break;
case State2:
action1;
cur_state = State0;
break;
default:break;
}
}
void event1func(void)
{
switch(cur_state)
{
case State0:
action4;
cur_state = State1;
break;
default:break;
}
}
void event2func(void)
{
switch(cur_state)
{
case State0:
action5;
cur_state = State2;
break;
case State1:
action6;
cur_state = State0;
break;
default:break;
}
}
Question 1: Comparison of STM32F407 VS STM32F103 main functions and resources?
Reference: Comparison of STM32F407 VS STM32F103 main functions and resources
Original text Source: https://juyou.blog.csdn.net/article/details/116021595
