NAPI NAPI is the event handling mechanism used by the Linux networking stack. Today, the term “NAPI” no longer represents any specific meaning [1]. In basic operations, devices notify the host of new events via interrupts. The host then schedules a NAPI instance to handle these events. Additionally, devices can poll for events through NAPI … Read more
The demands of embedded development programming are ever-changing. To achieve system stability and code reusability, high cohesion and low coupling must be maintained.It is generally believed that time-consuming operations cannot be executed within interrupts, as this would affect system stability. For programs with an operating system, interrupt handling can be divided into two parts through … Read more
In the dual-core architecture of the ESP32, the interrupt handling mechanism is key to achieving efficient real-time response. The ESP32 supports multicore interrupt handling (Core 0 and Core 1), but it needs to be combined with FreeRTOS task scheduling and synchronization mechanisms to fully leverage its performance. Below are the core technologies, configuration methods, and … Read more
Abstract Real-Time Operating Systems (RTOS) and Operating Systems (OS) both provide the capability to set thread priorities. We assign a unique priority to each thread based on the software functional architecture, thereby creating a hierarchy of threads within the system. However, this principle of assigning unique priorities can lead to issues, as assigning a unique … Read more
The packet reception process of the Linux network card is as follows: The network card receives the data packet. The data packet is moved from the network card hardware buffer to the server memory (using DMA, without going through the CPU). A hardware interrupt notifies the CPU to process it. The CPU notifies the kernel … Read more
In this article (How to Trigger User-Mode Events from Interrupt Handling Functions), we mentioned notifying a user-mode event in the WDF driver’s interrupt handling function using the KeSetEvent function, waking up the user-mode program to read the Timer’s count value. However, since the kernel function KeSetEvent is required to run at an IRQL less than … Read more
In the article on interrupt handling in drivers, we introduced how to add logic for handling periodic Timer interrupts in the driver for our simulated PCIe device. To test the Timer counting functionality, we also created a user-space test program that reads the Timer’s count register every second. While this approach can test whether the … Read more
In this article, we add a periodic Timer to the PCIe device previously simulated in Qemu. Once this Timer is enabled, it will trigger an MSI interrupt to the Qemu virtual machine every second. To verify that this interrupt function works correctly, we need to add interrupt handling capabilities to the driver for this PCIe … Read more
Recently, while simulating MSI-X interrupts using QEMU, I found that many people do not fully understand MSI-X interrupts. Below, I will analyze this based on the Linux kernel version 6.1.26 source code. 1. MSI-X Specification in the PCIe Protocol 1.1 MSI-X Capability in PCIe Configuration Space Capability According to the PCIe 3.0 specification, the MSI-X … Read more
1. Overview of CPU I/O Capabilities The CPU not only has computational capabilities but also needs to exchange data with external devices, a capability known as I/O (Input/Output) capability. Typical I/O operations in a computer system include: Keyboard input Display output Disk read/write Network communication, etc. 2. Two Core Issues in Peripheral Interaction 1. Peripheral … Read more