NAND Flash Prices Expected to Stabilize and Rise in Q4

This article is brought to you by Semiconductor Industry Insights (ID: ICVIEWS). Spot prices have already begun to recover. According to TrendForce, NAND Flash suppliers are expected to increase production cuts in Q4 to accelerate inventory reduction. It is estimated that the average price of NAND Flash in Q4 may stabilize or slightly increase, with … Read more

Weekly Market Update: Stable Price Increases for High-Capacity NAND Flash; How is the DRAM Spot Market Performing?

▲ Click on “Global Semiconductor Observation” above to follow our public account Part 1 DRAM Spot Prices Remain Flat This week, the DRAM spot market is quiet. Even though the official prices from manufacturers have seen slight increases, they have not stimulated market purchasing momentum, primarily due to poor end-user demand. Most factories are consuming … Read more

NAND Flash Prices Decline by 6% in 2018; New Devices and Demand for 256GB Capacity May Bring Opportunities

Due to the shortage and price increase of NAND Flash in 2016 and the first half of 2017, the demand in markets such as smartphones and SSDs weakened in the second half of 2017, exacerbated by the seasonal effects at the end of the year. At the beginning of 2018, the prices of NAND Flash-related … Read more

Simple and Efficient Encryption Algorithm TEA Implementation in Go

Click the blue “Go Language Chinese Network” above to follow, and learn Go together every day 1. What is the TEA Encryption Algorithm TEA (Tiny Encryption Algorithm) is a simple and efficient encryption algorithm, known for its fast encryption and decryption speed and simple and efficient implementation. This article contains a lot of code; if … Read more

Single-Core CPU Cracks Post-Quantum Encryption Algorithm in One Hour

Researchers from KU Leuven have proposed an efficient key recovery attack method against the SIDH protocol, capable of breaking the SIKE post-quantum cryptographic algorithm using a standard single-core CPU in just one hour. The key encapsulation mechanism is a protocol that securely exchanges symmetric keys using asymmetric cryptographic techniques. SIKE (Supersingular Isogeny Key Encapsulation) is … Read more

Dynamic Intelligent Modeling Methods for Real-Time Flood Control Scheduling of Reservoir Groups

Li, J., Zhong, P., Yang, M., Zhu, F., Chen, J., Xu, B., Liu, W. (2019). Dynamic and Intelligent Modeling Methods for Joint Operation of a Flood Control System. Journal of Water Resources Planning and Management. 145, 0401904410. https://doi.org/10.1061/(ASCE)WR.1943-5452.0001110 Li, J., Zhong, P., Yang, M., Zhu, F., Chen, J., Liu, W., Xu, S. (2020). Intelligent identification … Read more

Chapter 6 Low Power Design Analysis (Part 1) – The Theory and Practice of IR Drop and EM

With the increase in device density and clock frequency of chips under advanced processes, power consumption has also significantly increased. At the same time, the supply voltage and transistor threshold voltage have been reduced, leading to significant leakage current. High power consumption can cause excessive temperature during device operation, reducing reliability due to electromigration and … Read more

Fundamentals of Low-Power Design: A Comprehensive Analysis of Multi-Bit Cells

This article was originally published in the Zhihu column [The Path of Digital IC Backend Engineers]. Multi-bit cells have been widely used in numerous chip designs as a means to control power consumption, and various EDA tools provide extensive and comprehensive support for them. Today, we will start with the basic structure and principles of … Read more

Low Power Design Methods – Overview of Power Gating (Part 1)

Leakage power consumption has increased with each generation of CMOS technology. This leakage power not only poses a serious challenge for battery-powered or portable products but is also becoming an issue that wired devices such as servers, routers, and set-top boxes must address. To reduce the total leakage power consumption of chips, it is best … Read more

Low Power Design Methods – Power Gating Design (Part 3)

State Retention and Restoration Methods Continuing from the previous text Low Power Design Methods – Power Gating Design (Part 1) Low Power Design Methods – Power Gating Design (Part 2) Given the power switch structure and isolation strategy, power gating can be applied to logic blocks. However, unless a retention strategy is employed, all state … Read more