What Tests Are Required for Chips?

Source: Content from WeChat public account “Hushan Capital“, thank you.

The most basic steps in making a chip are design -> tape-out -> packaging -> testing. The cost composition of a chip is generally 20% labor cost, 40% tape-out, 35% packaging, and 5% testing【For advanced processes, tape-out costs may exceed 60%】.

Testing is actually the cheapest step among all stages of chip production. In this fiercely competitive market where every company is shouting “Cost Down”, labor costs are rising year by year, wafer fabs and packaging factories are dominating the secondary market, and testing seems to be the only area that is not so difficult to tackle. The burden of cost reduction falls on testing.

However, upon careful calculation, if testing saves 50%, the total cost only saves 2.5%. If tape-out or packaging saves 15%, testing is almost free.But testing is the last line of defense for product quality. Without good testing, the product’s PPM【Parts Per Million failure rate】 will be too high, and returns or compensations are far from what 5% of the cost can represent.

What Tests Are Required for Chips?

Mainly divided into three categories:Chip functional testing, performance testing, and reliability testing are all essential for a chip product to be launched.

Functional Testing Checks If the Chip Works Correctly

Performance Testing Checks How Good the Chip Is

Reliability Testing Checks If the Chip Is Durable

Functional testing assesses the chip’s parameters, indicators, and functions; in layman’s terms, it’s about seeing if the precious baby you’ve been nurturing for ten months is a mule or a horse.

Performance testing is necessary because, during the chip manufacturing process, there are countless potential steps that can introduce defects. Even within the same batch of wafers and packaged products, chips can vary in quality, thus requiring screening. In simple terms, it’s about picking stones out of eggs and discarding the “stone” chips.

Reliability testing is conducted after the chip has passed functional and performance testing. It assesses whether the chip can withstand annoying static electricity in winter, function properly during thunderstorms, hot summer days, or snowstorms, and whether the chip can last a month, a year, or ten years, etc. All of these need to be evaluated through reliability testing.

What Methods Do We Have to Achieve These Tests?

Testing Methods:Board-level testing, wafer CP testing, post-packaging FT testing, system-level SLT testing, and reliability testing, employing multiple strategies.

Board-level testing is mainly used for functional testing, using a PCB board + chip to create a “simulated” chip working environment. It connects all the chip interfaces to test its functionality or see if it can operate normally under various harsh conditions.The main equipment needed includes instruments, and the main hardware to be created is the EVB evaluation board.

Wafer CP testing is commonly used in functional and performance testing to determine if the chip functions normally and to screen out defective chips from the wafer.CP【Chip Probing】, as the name suggests, involves using probes to “poke” the chips on the wafer, inputting various signals into the chip, capturing its output responses for comparison and calculation. Some special scenarios may also use it to configure and adjust the chip【Trim】.The main equipment required includes automatic test equipment【ATE】 + prober + instruments, and the hardware to be created is the probe card【Probe Card】.

Post-packaging FT testing is commonly used in functional, performance, and reliability testing to check if the chip functions normally and whether any defects occurred during packaging, and it helps in reliability testing to check if the chip can still work after being subjected to “fire, snow, and thunder”.The main equipment needed includes automatic test equipment【ATE】 + handler + instruments, and the hardware to be created includes load boards【Loadboard】 + test sockets【Socket】, etc.

System-level SLT testing is often used in functional, performance, and reliability testing, typically serving as a supplement to FT testing. As the name suggests, it tests the chip in a system environment, meaning the chip runs its functions in its normal operating environment to check its performance. The downside is that it can only cover a portion of the functions, so its coverage is relatively low, which is why it generally serves as a supplementary method to FT.The main equipment needed includes a handler, and the hardware to be created includes a system board【System Board】 + test sockets【Socket】.

Reliability testing mainly involves subjecting the chip to various harsh environments, such as ESD static electricity, which simulates a human body or industrial entity applying a sudden high voltage to the chip.For instance, aging HTOL【High Temperature Operating Life】 involves accelerating chip aging at high temperatures to estimate its lifespan.Additionally, HAST【Highly Accelerated Stress Test】 tests the moisture resistance of the chip packaging, where the product is subjected to extreme temperature, humidity, and pressure conditions to see if moisture can seep into the package through the interface between the colloid or colloid and the wire frame, thereby damaging the chip.Of course, there are many more methods, too numerous to list, which will be explained in future columns.

Diagram of the Relationship Between Testing Categories and Testing Methods

Conclusion and Outlook

Chip testing is by no means a simple matter of picking stones out of eggs; it requires meticulous control and participation throughout the entire process.

From the start of chip design, considerations should be made on how to test, whether to add DFT【Design for Test】 design, and whether self-testing through functional design【FuncBIST】 can reduce reliance on peripheral circuits and testing equipment.

When chip verification begins, the final testing vectors should be considered, and the verification test bench should be written in a cycle-based manner, making it easier to convert generated vectors and avoid data omissions, etc.

During the chip tape-out stage, the testing plan should be finalized, and the development of ATE testing programs and CP/FT hardware should be executed in parallel to ensure that testing begins as soon as the chip comes off the wafer production line, greatly shortening the chip development cycle.

Finally, testing becomes even more critical during mass production. How to supervise and control testing yield, how to respond to customer complaints and low PPM situations, and how to continuously optimize testing processes to improve efficiency, reduce testing time, and lower testing costs are all crucial.

Thus, chip testing is not just a cost issue; it is actually an art of balancing quality + efficiency + cost!

*Disclaimer: This article is an original work by the author. The content represents the author’s personal views. Semiconductor Industry Observer reproduces it solely to convey a different perspective and does not imply endorsement or support of this viewpoint. If there are any objections, please feel free to contact Semiconductor Industry Observer.

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What Tests Are Required for Chips?

What Tests Are Required for Chips?

What Methods Do We Have to Achieve These Tests?

Conclusion and Outlook

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