In the field of chip design, ECO (Engineering Change Order) is a key concept. Below, we will detail its definition, role, implementation process, and practical applications:
1. Definition of ECO
ECO refers to a localized circuit modification plan implemented after the chip design has completed tape-out, addressing minor design defects or changes in functional requirements discovered in the manufactured chip. It does not require a complete redesign and tape-out of the chip but instead modifies the chip’s metal layer connections, configures programmable logic units (such as FPGAs), or adjusts storage units (such as ROM or registers) to correct or optimize the chip’s functionality.
2. Core Functions of ECO
Fixing Design Defects
If logical errors, timing violations (such as setup/hold time violations), or functional deficiencies are discovered after tape-out, the circuit can be modified through ECO, avoiding the high costs of re-tape-out (which can reach millions to tens of millions of dollars).
For example, if a processor chip is found to have a data consistency issue in the cache controller during testing, an additional control signal path can be added through ECO to fix it.
Meeting Requirement Changes
When customer requirements change temporarily (such as adding new interface protocols or optimizing power modes), there is no need to redesign the chip; ECO can quickly implement functional iterations.
For instance, if a 5G chip needs to support a new frequency band protocol before mass production, the logic of the RF front-end configuration register can be modified through ECO.
Reducing Costs and Time
Re-tape-out takes months and is extremely costly; ECO can shorten the modification cycle to weeks while saving over 90% of the costs, making it especially suitable for urgent corrections before mass production.
Supporting Chip Version Iteration
When different models (such as high and low power versions) are derived from the same chip platform, ECO can adjust certain circuits (such as disabling unused modules) to avoid redundant design.
3. Implementation Methods and Technical Means of ECO
Depending on the chip type (ASIC or FPGA) and process characteristics, ECO is mainly implemented through the following methods:
1. Hardware-Level Modifications
Metal Layer Connection Adjustments
In ASICs, by adding or modifying the wiring of the metal layers (which requires process support for multiple metal layers), the signal path can be changed. For example, disconnecting an erroneous clock signal line and reconnecting it to the correct clock buffer.
Fuse or Antifuse Programming
Using fuse structures (physical fusing) or antifuses (breaking down the insulating layer) to achieve permanent modifications to circuit connections, commonly seen in one-time programmable (OTP) chips.
Programmable Logic Unit Configuration
In FPGAs, the logic element (LE/LUT) connection relationships or register states can be modified by rewriting the configuration file (.bit file).
2. Software-Level Configuration
Register/ROM Parameter Adjustments
By modifying the default values of internal chip registers or the microcode stored in ROM, functional logic can be corrected. For example, updating the enumeration protocol parameters of a USB controller.
Clock/Power Domain Control
Adjusting clock division ratios or power domain switching strategies to optimize power consumption or timing (such as reducing the operating frequency of non-critical modules).
4. Implementation Process of ECO
Problem Identification and Assessment
Through chip testing (such as ATE testing, FPGA prototype verification), the defect location is determined, and the feasibility of the ECO modification is assessed (such as whether it involves the underlying circuit and whether there are sufficient metal layer wiring resources).
Design Modification Plan
Using EDA tools (such as Synopsys IC Compiler, Cadence Virtuoso) to generate ECO scripts, defining the netlist nodes or wiring paths that need to be modified.
Simulation Verification
Performing timing simulation, functional simulation, and DRC (Design Rule Check) on the ECO plan to ensure that the modifications do not introduce new issues.
Physical Implementation and Verification
Marking the metal layer locations of the ECO modifications on the chip layout, generating GDSII files, and creating masks for localized modifications for subsequent chip processing.
Pre-Mass Production Testing
Comprehensive testing of the chip samples after ECO modifications is conducted to confirm that defects are repaired and functionality is normal before mass production can commence.
After going through this series of processes and considerations, we can finally complete the ECO, ensuring a smooth tape-out and obtaining a good chip.
5. Limitations of ECO
Limited Modification Scope: It is only suitable for small-scale modifications (such as a few gate circuits or a single signal path) and cannot handle large-scale architectural changes (such as adding a new processor core).
Increased Testing Complexity: The ECO version must be tested in parallel with the original version to ensure consistency and compatibility of the modifications.
6. Conclusion
ECO is a key technology in the chip design process that reduces costs and shortens iteration cycles. Its core value lies in quickly responding to design defects and requirement changes through localized hardware or software modifications, which is especially significant for enhancing chip R&D efficiency and market competitiveness at advanced process nodes.