Using the JTAG to AXI Master IP Core (Part 2)

0. Visual China

Visual China Contracted Photographer Horizon-Alhambra Sunset

1. Practical Tutorial for Using the JTAG to AXI Master IP Core

The core value of the JTAG to AXI Master lies in its ability to achieve flexible AXI transaction control through Tcl scripts.Reset JTAG to AXI Master:

reset_hw_axi [get_hw_axis hw_axi_1]

Write Transaction Example:

# Create write transactioncreate_hw_axi_txn write_txn [get_hw_axis hw_axi_1] \   -address 40000000 \   -data 12345678 \   -type write
# Execute write transactionrun_hw_axi write_txn

Read Transaction Example:

# Create read transactioncreate_hw_axi_txn read_txn [get_hw_axis hw_axi_1] \   -address 40000000 \   -type read
# Execute read transactionrun_hw_axi read_txn

Burst Transfer Example:

# AXI4 burst write with 8 data itemscreate_hw_axi_txn burst_write [get_hw_axis hw_axi_1] \   -address 40000000 \   -data {11111111 22222222 33333333 44444444 55555555 66666666 77777777 88888888} \   -len 8 -type write
# Queue multiple transactionsrun_hw_axi txn1 txn2 txn3 -queue

2. Encapsulating Tcl Scripts

To improve debugging efficiency, common operations can be encapsulated as Tcl procedures. For example, I encapsulated the read and write register operations into the following script:

proc ReadReg { Addr } {  puts "Start reading operation"  set address [format "0x%08X" $Addr]  set len 1  create_hw_axi_txn read_txn [get_hw_axis hw_axi_1] -type read -address $address -len $len  run_hw_axi [get_hw_axi_txns read_txn]  set read_proc [list [report_hw_axi_txn [get_hw_axi_txns read_txn]]];  puts $read_proc  set read_status_value [lindex $read_proc 0 1]  delete_hw_axi_txn [get_hw_axi_txns read_txn]  puts $read_status_value  return $read_status_value}proc WriteReg { Addr data} {  set len 1  set address [format "0x%08X" $Addr]  set data [format "0x%08X" $data]  create_hw_axi_txn write_txn [get_hw_axis hw_axi_1] -type write -address $address -len $len -data $data  run_hw_axi [get_hw_axi_txns write_txn]  delete_hw_axi_txn [get_hw_axi_txns write_txn]}

Importing Tcl Scripts:Reading Registers:

// Read register 0x0 of peri_reg_config moduleReadReg 0Start reading operationINFO: [Labtoolstcl 44-481] READ DATA is: 20251119
// Read register 0x0 of system_reg_config moduleReadReg 0x10000000Start reading operationINFO: [Labtoolstcl 44-481] READ DATA is: 20251117

Read Bus Timing Diagram:Writing Registers:

// Write register 0x4 of peri_reg_config moduleWriteReg 0x4 0x1234INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00001234
// Read register 0x4 of peri_reg_config moduleReadReg 4Start reading operationINFO: [Labtoolstcl 44-481] READ DATA is: 00001234
// Write register 0x4 of system_reg_config moduleWriteReg 0x10000004 0x4321INFO: [Labtoolstcl 44-481] WRITE DATA is: 0x00004321
// Read register 0x4 of system_reg_config moduleReadReg 0x10000004Start reading operationINFO: [Labtoolstcl 44-481] READ DATA is: 00004321

Write Bus Timing Diagram:

Using the JTAG to AXI Master IP Core (Part 2)

3. Previous Review

[Xilinx IP] JTAG to AXI Master (Part 1) Detailed Explanation of IP Core