1. What Makes RISC-V Different from Other Open Architectures
If we only evaluate based on the criteria of “free” or “open”, the RISC-V architecture is not the first processor architecture to achieve either of these.
Before we begin, let us analyze the differences of RISC-V architecture and why other open architectures have not achieved sufficient success by discussing several representative open architectures.
1.1 The People’s Hero – OpenRISC
OpenRISC is an open-source RISC processor based on the GPL license provided by the OpenCores organization.
OpenRISC has the following characteristics:
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Uses a free and open 32/64-bit RISC architecture.
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Implements processor source code based on this architecture using Verilog HDL (hardware description language).
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Has a complete toolchain.
OpenRISC has been applied in many company projects. It can be said that OpenRISC is a widely used open-source processor implementation.
The shortcoming of OpenRISC is that it focuses on implementing an open-source CPU Core rather than defining an open instruction set architecture, so its architecture development is not complete, and the definition of the instruction set does not possess the advantages mentioned in the previous section regarding RISC-V architecture, nor has it risen to the level of establishing a dedicated foundation. OpenRISC is often viewed more as an open-source Core than a beautiful instruction set architecture. Additionally, the GPL license of OpenRISC means that all instruction set modifications must be open-source (whereas RISC-V does not have this constraint).
1.2 The Aristocrat – SPARC
As one of the classic RISC microprocessor architectures, SPARC was designed by Sun Microsystems in 1985. SPARC is also a registered trademark of SPARC International, a company established in 1989 to promote the SPARC architecture and conduct compatibility testing for it. To promote the SPARC ecosystem, SPARC International opened the standards and licensed them to multiple manufacturers, including Texas Instruments, Cypress Semiconductor, and Fujitsu. Since SPARC architecture is also completely open, there have been fully open-source LEON processors. Moreover, Sun also promoted the SPARC v8 architecture to become an IEEE standard (IEEE Standard 1754-1994) in 1994.
Since SPARC architecture was originally designed for the server domain, its most notable feature is having a large register window, requiring SPARC architecture processors to implement anywhere from 72 to 640 general-purpose registers, each with a width of 64 bits, forming a series of register groups known as the register window.
This register window architecture can quickly respond to function calls and returns by switching between different groups of registers, thus producing very high performance. However, this architecture is not suitable for PC and embedded domain processors due to its large power and area costs. Additionally, SPARC architecture lacks modularity, making it impossible for users to trim and select. It is difficult to serve as a general-purpose processor architecture to replace commercial x86 and ARM architectures.
Designing such large server CPU chips is not something ordinary companies or individuals can engage in, and companies capable of designing such large CPUs have no need to invest huge costs to challenge the dominance of x86. With the decline of Sun, the SPARC architecture has now basically faded from public view. Interested readers can search for the article “Goodbye SPARC Processor, Goodbye Sun” online.
1.3 The Ivy League Graduate – RISC-V
RISC-V was born at the University of California, Berkeley.
For many years, multiple free or open architectures have emerged in the CPU field, and many universities have launched various instruction set architectures in research projects. Therefore, when I first heard about RISC-V, I thought it was just another toy or purely academic research project and did not pay much attention to it.
It wasn’t until I personally read through the RISC-V architecture documentation that I was amazed by its advanced design philosophy. The various advantages of the RISC-V architecture have also received praise from many professionals and led to numerous commercial companies joining in. The formal launch of the RISC-V foundation in 2016 has made a significant impact in the industry. All these factors have made RISC-V the most revolutionary open processor architecture to date.
2. Simplicity is Beauty – The Design Philosophy of RISC-V Architecture
As an instruction set architecture, before introducing the details, let us first understand the design philosophy. The so-called design philosophy refers to a strategy that is advocated, for example, we are familiar with the design philosophy of Japanese cars being fuel-efficient and American cars being powerful and ostentatious. What is the design philosophy of RISC-V architecture? It is “Simplicity is Beauty”.
One design principle I highly advocate is: simplicity is beauty, and simplicity signifies reliability. Countless real-world cases have proven the truth that “simplicity means reliability”; conversely, the more complex a machine is, the more likely it is to fail.
The principle of simplicity is evident in practical IC design work. I have seen the simplest design achieve safety and reliability, while the most complex design has struggled to stabilize over time. The simplest designs are often the most reliable, as repeatedly verified in most project practices.
The nature of IC design is very unique; its final output is a chip, and the design and manufacturing cycle of a chip are long, making it difficult to upgrade and patch like software code. Each revision of a chip from design to delivery takes several months. Moreover, the cost of manufacturing a chip is high, ranging from hundreds of thousands to millions of dollars. These characteristics make the cost of trial and error in IC design extremely high; thus, effectively reducing the occurrence of errors is crucial.
Modern chip designs are becoming larger and more complex, which does not mean that designers should avoid using complex technologies; rather, they should focus on applying the best technologies to critical scenarios and, where possible, choose simpler implementation solutions.
When I first read the RISC-V architecture documentation, I couldn’t help but applaud and marvel at its design philosophy, which constantly emphasizes that its design philosophy is “Simplicity is Beauty”, aiming to make hardware implementation sufficiently simple through architecture definition. Its philosophy of simplicity can be easily observed in several aspects, which will be discussed in detail in the following sections.
2.1 Light as a Feather – The Length of the Architecture
In the processor field, the mainstream architectures are x86 and ARM. I have previously participated in the design of ARM architecture application processors, so I need to read ARM’s architecture documentation. Familiar readers should understand its length. After decades of development, the modern x86 and ARM architecture documents span hundreds to thousands of pages. When printed, they can be half a desk high, truly a “monumental work”.
The reason why the modern x86 and ARM architecture documents are so lengthy, with numerous versions, is primarily due to the continuous development and maturity of modern processor architecture technology alongside their architectural development.
Moreover, as commercial architectures, to maintain backward compatibility, they must retain many outdated definitions or awkwardly accommodate existing technological components when defining new architecture parts. Over time, this leads to excessive length.
So, can modern mature architectures choose to restart and redefine a simpler architecture? It is almost impossible. One important reason is that they cannot maintain backward compatibility, making it unacceptable to users. Imagine if we bought a new computer or phone with a new processor and none of the previous software could run, causing it to become a brick; that would certainly be unacceptable.
However, the newly introduced RISC-V architecture has the advantage of being a latecomer. Since computer architecture has matured over many years, the issues exposed during this maturation process have been thoroughly studied, allowing the new RISC-V architecture to avoid these pitfalls and not bear the historical burden of backward compatibility; it can be said to be light as a feather.
Currently, the “RISC-V architecture documents” are divided into “Instruction Set Document” (riscv-spec-v2.2.pdf) and “Privileged Architecture Document” (riscv-privileged-v1.10.pdf). The length of the “Instruction Set Document” is 145 pages, while the “Privileged Architecture Document” is only 91 pages. Engineers familiar with architecture can read through them in just one or two days. Although the “RISC-V architecture documents” are continually being enriched, compared to the “x86 architecture documents” and “ARM architecture documents”, the length of RISC-V can be described as extremely concise and to the point.
Interested readers can download the documents for free from the RISC-V Foundation website (https://riscv.org/specifications/) without registration, as shown in Figure 1.
Figure 1: Architecture documents on the RISC-V Foundation website
2.2 Flexibility – Modular Instruction Set
One of the biggest differences of RISC-V architecture compared to other mature commercial architectures is that it is a modular architecture. Therefore, RISC-V architecture is not only concise and precise, but also its different parts can be organized in a modular way, attempting to meet various application needs through a unified architecture.
This modularity is not found in x86 and ARM architectures. For example, the ARM architecture is divided into three series: A, R, and M, which are targeted at Application (application operating systems), Real-Time (real-time), and Embedded (embedded) fields, respectively, and are not compatible with each other.
However, the modular RISC-V architecture allows users to flexibly choose different module combinations to meet different application scenarios, making it suitable for all ages. For example, for small area low-power embedded scenarios, users can choose the RV32IC instruction set, using only Machine Mode; while for high-performance application operating system scenarios, they can choose the RV32IMFDC instruction set, using both Machine Mode and User Mode. Their common components can be mutually compatible.
2.3 Concentrated Essence – Number of Instructions
The concise architecture and modular philosophy make the number of instructions in the RISC-V architecture very simple. The basic number of RISC-V instructions is only over 40, and with other modular extension instructions, there are only several dozen instructions in total.
3. Overview of RISC-V Instruction Set Architecture
This chapter will briefly introduce various features of the RISC-V instruction set architecture.
3.1 Modular Instruction Subsets
The RISC-V instruction set is organized in a modular manner, with each module represented by a letter. The most basic and only mandatory instruction set part of RISC-V is represented by the letter I, which is the basic integer instruction subset. By using this integer instruction subset, a complete software compiler can be implemented. Other instruction subset parts are optional modules, with representative modules including M/A/F/D/C, as shown in Table 1.
Table 1: RISC-V Modular Instruction Set
To improve code density, the RISC-V architecture also provides an optional “Compressed” instruction subset, represented by the letter C. The instruction encoding length of compressed instructions is 16 bits, while the length of ordinary non-compressed instructions is 32 bits. This specific combination of modules “IMAFD” is also known as the “general” combination, represented by the letter G. Therefore, RV32G represents RV32IMAFD, and similarly, RV64G represents RV64IMAFD.
To further reduce area, RISC-V architecture also provides an “Embedded” architecture, represented by the letter E. This architecture is primarily used in extremely low area and power scenarios. This architecture only requires support for 16 general-purpose integer registers, while the ordinary architecture requires support for 32 general-purpose integer registers.
Through the above modular instruction set, different combinations can be chosen to meet different applications. For example, for low area and low power embedded scenarios, RV32EC architecture can be selected; while for large 64-bit architectures, RV64G can be selected.
In addition to the modules mentioned above, there are several other modules, including L, B, P, V, and T, among others. Most of these extensions are still being refined and defined, and thus will not be discussed in detail in this article.
3.2 Configurable General Register Groups
The RISC-V architecture supports either 32-bit or 64-bit architectures; the 32-bit architecture is represented by RV32, with each general-purpose register having a width of 32 bits; the 64-bit architecture is represented by RV64, with each general-purpose register having a width of 64 bits.
The integer general register group of the RISC-V architecture contains 32 (I architecture) or 16 (E architecture) general integer registers, with integer register 0 reserved as constant 0, and the other 31 (I architecture) or 15 (E architecture) as ordinary general integer registers.
If the floating-point module (F or D) is used, an additional independent floating-point register group is required, containing 32 general floating-point registers. If only the floating-point instruction subset of the F module is used, the width of each general floating-point register is 32 bits; if the floating-point instruction subset of the D module is used, the width of each general floating-point register is 64 bits.
3.3 Organized Instruction Encoding
In a pipeline, being able to read the general register group as early and quickly as possible is often one of the design goals of processor pipelines, as this can improve processor performance and optimize timing. This seemingly simple principle is difficult to achieve in many existing commercial RISC architectures because, after years of repeated modifications with new instructions being constantly added, the positions of register indexes in their instruction encoding have become very messy, burdening the decoder.
Thanks to the latecomer advantage and the lessons learned from years of processor development, RISC-V’s instruction set encoding is very organized, with the indexes of the general registers required by the instruction fixed in specific positions, as shown in Figure 2. Therefore, the instruction decoder can easily decode the register index and then read the general register group (Register File, Regfile).
Figure 2: Organized instruction encoding format of RV32I
3.4 Simplified Memory Access Instructions
Like all RISC processor architectures, the RISC-V architecture uses dedicated memory read (Load) and memory write (Store) instructions to access memory. Other ordinary instructions cannot access memory; this architecture is a common basic strategy of RISC architectures, which simplifies the hardware design of processor cores.
The basic unit of memory access is a byte (Byte). The memory read and write instructions of RISC-V support operations in units of one byte (8 bits), half-word (16 bits), and word (32 bits); if it is a 64-bit architecture, it can also support memory read and write operations in units of double-word (64 bits).
The memory access instructions of the RISC-V architecture have the following significant features:
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To improve the performance of memory read and write operations, the RISC-V architecture recommends using address-aligned memory read and write operations, but it also supports unaligned memory operations; the processor can choose to support this either through hardware or software.
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As the mainstream application now is little-endian format, the RISC-V architecture only supports little-endian format. This article does not delve into the definitions and differences of little-endian and big-endian formats; beginners who are not familiar with this can look up and study it themselves.
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Many RISC processors support address increment or decrement modes. While this increment or decrement mode can enhance the performance of the processor when accessing consecutive memory address ranges, it also complicates the design of the processor. RISC-V architecture’s memory read and write instructions do not support address increment and decrement modes.
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The RISC-V architecture adopts a relaxed memory model, meaning that it does not impose order on the execution of memory read and write instructions accessing different addresses unless explicitly masked by a memory barrier (Fence) instruction.
These choices clearly reflect RISC-V’s efforts to simplify the basic instruction set, thereby simplifying hardware design. The definitions of the RISC-V architecture are very reasonable, achieving flexibility. For example, for low-power simple CPUs, very simple hardware circuits can be used for design; while for high-performance superscalar processors, dynamic hardware scheduling capabilities can be employed to improve performance.
3.5 Efficient Branch and Jump Instructions
The RISC-V architecture has two unconditional jump instructions (Unconditional Jump), jal and jalr. The Jump and Link instruction jal can be used for subroutine calls while storing the return address in the link register (Link Register: served by a general integer register). The Jump and Link-Register instruction jalr can be used for subroutine return instructions by using the base address register from the previously saved link register of the jal instruction to return from the subroutine.
The RISC-V architecture has six conditional jump instructions (Conditional Branch). These conditional jump instructions directly use two integer operands, comparing them, and if the comparison condition is met, a jump occurs. Thus, this type of instruction combines comparison and jump operations into a single instruction.
In contrast, many other RISC architectures require two separate instructions. The first instruction performs the comparison, and the result is stored in a status register; the second instruction uses the jump instruction, which checks the result stored in the status register from the previous instruction, jumping if true. Compared to this, RISC-V’s conditional jump instructions not only reduce the number of instructions but also simplify the hardware design.
For low-end CPUs that do not have hardware branch predictors, RISC-V architecture explicitly requires the use of a default static branch prediction mechanism to ensure performance, which predicts that if the conditional jump instruction is a backward jump, it will be predicted as a “jump”; if it is a forward jump, it will be predicted as “not jump”. RISC-V architecture requires compilers to compile assembly code according to this default static branch prediction mechanism, allowing low-end CPUs to achieve decent performance.
To simplify hardware design, the RISC-V architecture defines that the target offsets of all conditional jump instructions (relative to the current instruction address) are signed numbers, with their sign bits encoded in fixed positions. Therefore, this static prediction mechanism can be easily implemented in hardware, where the hardware decoder can easily find this fixed position and determine whether it is a positive or negative number, predicting jumps accordingly. Of course, high-end CPUs equipped with hardware branch predictors can adopt advanced dynamic branch prediction mechanisms to ensure performance.
3.6 Simplified Subroutine Calls
To understand this section, one must first introduce the process of calling sub-functions in general RISC architectures, which involves:
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Upon entering a sub-function, a store instruction is needed to save the current context (values of general registers, etc.) to the system memory stack area, a process usually referred to as “saving the context”.
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Upon exiting the subroutine, a load instruction is needed to read the previously saved context (values of general registers, etc.) from the system memory stack area, a process usually referred to as “restoring the context”.
The processes of “saving context” and “restoring context” are typically completed by instructions generated by the compiler, and developers using high-level languages (such as C or C++) do not need to worry about this too much. In high-level language programs, one simply needs to write a sub-function call, but the underlying processes of “saving context” and “restoring context” are indeed happening (these “saving context” and “restoring context” assembly instructions can be seen in the compiled assembly code).
To accelerate the processes of “saving context” and “restoring context”, some RISC architectures have invented instructions to write multiple registers to memory at once (Store Multiple) or read multiple registers from memory at once (Load Multiple). The advantage of these instructions is that a single instruction can accomplish multiple tasks, thereby reducing the number of assembly instructions and saving code space. However, the downside of such “Load Multiple” and “Store Multiple” instructions is that they complicate the hardware design of CPUs, increasing hardware overhead, and may impair timing, preventing the CPU’s clock frequency from being increased; I have suffered from this when designing such processors.
The RISC-V architecture, however, abandons the use of such “Load Multiple” and “Store Multiple” instructions. It explains that if there are concerns about the number of “saving context” and “restoring context” instructions, a shared library (specifically for saving and restoring context) can be used, thus eliminating the need to insert varying numbers of “saving context” and “restoring context” instructions in each sub-function call.
This choice reaffirms RISC-V’s pursuit of hardware simplicity, as abandoning “Load Multiple” and “Store Multiple” instructions can significantly simplify CPU hardware design. Low-power small-area CPUs can adopt very simple circuits for implementation, while high-performance superscalar processors, with strong dynamic scheduling capabilities, can utilize powerful branch prediction circuits to ensure that the CPU can quickly jump to execute, thus allowing the use of shared libraries to reduce code volume while achieving high performance.
3.7 Unconditional Code Execution
Many early RISC architectures invented instructions with condition codes, where the condition code (Conditional Code) is represented in the leading bits of the instruction, and the instruction is executed only if the corresponding condition code is true.
The benefit of encoding condition codes into instructions is that it allows compilers to compile short loops into condition code instructions rather than into branch jump instructions. This reduces the occurrence of branch jumps, thus minimizing the number of instructions; on the other hand, it avoids performance losses caused by branch jumps. However, the downside of such “conditional code” instructions is that they complicate CPU hardware design, increasing hardware overhead, and may impair timing, which I have also suffered from when designing such processors.
The RISC-V architecture abandons the use of such condition code instructions; for any conditional judgment, it uses ordinary conditional branch jump instructions. This choice again emphasizes RISC-V’s pursuit of hardware simplicity, as abandoning condition code instructions can significantly simplify CPU hardware design. Low-power small-area CPUs can use very simple circuits for implementation, while high-performance superscalar processors, with strong dynamic scheduling capabilities, can have powerful branch prediction circuits to ensure that the CPU can quickly jump to execute, achieving high performance.
3.8 No Branch Delay Slots
Many early RISC architectures adopted “branch delay slots”; the most representative is the MIPS architecture, which has been introduced in many classic computer architecture textbooks. A branch delay slot refers to one or several instructions immediately following each branch instruction that are not affected by the branch jump; regardless of whether the branch jumps, these subsequent instructions will always be executed.
The reason many early RISC architectures adopted branch delay slots was due to the simplicity of their processor pipelines at the time, which did not use advanced hardware dynamic branch predictors. Thus, using branch delay slots could achieve considerable performance benefits. However, this has made CPU hardware design extremely awkward, leaving CPU designers struggling.
The RISC-V architecture abandons branch delay slots, again reflecting RISC-V’s goal of simplifying hardware. Modern high-performance processors have very high accuracy in branch prediction algorithms and can utilize powerful branch prediction circuits to ensure that the CPU can accurately predict jumps, achieving high performance. For low-power small-area CPUs, eliminating the need to support branch delay slots greatly simplifies hardware and can further reduce power consumption and improve timing.
3.9 No Zero-Overhead Hardware Loops
Many RISC architectures also support zero-overhead hardware loop instructions, which involve direct hardware participation, setting certain loop count registers (Loop Count) to allow the program to loop automatically. Each iteration reduces the Loop Count by 1 until it reaches 0, at which point the loop exits.
The reason for inventing such hardware-assisted zero-overhead loops is that for loops (for i=0; i
However, there are trade-offs; such zero-overhead loop instructions significantly increase the complexity of hardware design. Therefore, zero-overhead loop instructions are completely contrary to RISC-V’s philosophy of simplifying hardware, and naturally, the RISC-V architecture does not use such zero-overhead loop instructions.
3.10 Simplified Arithmetic Instructions
In section 2.1 of this chapter, it was mentioned that the RISC-V architecture organizes different instruction subsets in a modular way. The basic integer instruction subset (represented by the letter I) supports operations including addition, subtraction, shifting, bitwise logical operations, and comparison operations. These basic arithmetic operations can achieve more complex operations (such as multiplication and division) through combinations or libraries, thus completing most software operations.
The integer multiplication and division instruction subset (represented by the letter M) supports operations including signed or unsigned multiplication and division. The multiplication operation can support multiplying two 32-bit integers to produce a 64-bit result, while the division operation can support dividing two 32-bit integers to yield a 32-bit quotient and a 32-bit remainder.
The single-precision floating-point instruction subset (represented by the letter F) and double-precision floating-point instruction subset (represented by the letter D) support operations including floating-point addition and subtraction, multiplication and division, multiply-accumulate, square root, and comparison, while also providing format conversion operations between integers and floating points, as well as between single and double precision floating points.
Many RISC architectures’ processors generate software exceptions when arithmetic instructions produce errors, such as overflow, underflow, subnormal floating-point numbers, and divide by zero. A special feature of the RISC-V architecture is that no exceptions are generated for any arithmetic instruction errors (including both integer and floating-point instructions); instead, a specific default value is generated, and certain status bits in the status register are set. The RISC-V architecture recommends that software find these errors through other means. This clearly reflects RISC-V’s philosophy of simplifying the basic instruction set, thereby simplifying hardware design.
3.11 Elegant Compressed Instruction Subset
The basic integer instruction subset of RISC-V (represented by the letter I) defines that all instruction lengths are uniformly 32 bits. This uniform instruction definition makes it very easy to design CPUs that only support integer instruction subsets. However, the uniform 32-bit encoded instructions can also lead to larger code size issues.
To meet certain scenarios that have higher requirements for code size (such as embedded fields), RISC-V defines an optional compressed (Compressed) instruction subset, represented by the letter C, or RVC. With the latecomer advantage, RISC-V planned for compressed instructions from the start, reserving sufficient encoding space, allowing 16-bit instructions and ordinary 32-bit instructions to be seamlessly interleaved without defining additional states in the processor.
Another special aspect of RISC-V compressed instructions is that the compression strategy for 16-bit instructions is to compress and rearrange the information from some of the most commonly used 32-bit instructions (for example, if an instruction uses two identical operand indexes, one of the index encodings can be omitted). Therefore, each 16-bit instruction can find its corresponding original 32-bit instruction. Consequently, the compilation of programs into compressed instructions can be completed at the assembler stage, significantly reducing the burden on the compiler toolchain.
RISC-V researchers conducted detailed code size analyses, as shown in Figure 3. The analysis results indicate that the code size of RV32C is reduced by 40% compared to RV32, and it performs well compared to architectures such as ARM, MIPS, and x86.
Figure 3: Comparison of code density across instruction set architectures (smaller data is better)
3.12 Privilege Modes
The RISC-V architecture defines three working modes, also known as privilege modes (Privileged Mode):
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Machine Mode: abbreviated as M Mode.
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Supervisor Mode: abbreviated as S Mode.
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User Mode: abbreviated as U Mode.
The RISC-V architecture defines M Mode as a mandatory mode, while the other two are optional modes. Different combinations of modes can achieve various systems.
The RISC-V architecture also supports several different memory address management mechanisms, including management mechanisms for physical and virtual addresses, enabling RISC-V architecture to support a range of systems from simple embedded systems (directly operating physical addresses) to complex operating systems (directly operating virtual addresses).
3.13 CSR Registers
The RISC-V architecture defines several Control and Status Registers (CSR) used to configure or record some operational states. CSR registers are internal registers within the processor core, using their own address encoding space that is entirely unrelated to memory addressing.
CSR registers are accessed using dedicated CSR instructions, including CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, and CSRRCI instructions.
3.14 Interrupts and Exceptions
The interrupt and exception mechanisms are often the most complex and critical parts of processor instruction set architectures. The RISC-V architecture defines a relatively simple and basic interrupt and exception mechanism but also allows users to customize and extend it.
3.15 Vector Instruction Subset
Although the RISC-V architecture has not yet formalized a vector instruction subset, the design concept for the RISC-V vector instruction subset is very advanced. Leveraging the latecomer advantage and the conclusions drawn from years of vector architecture development, the RISC-V architecture will use variable-length vectors instead of fixed-length SIMD instruction sets (such as ARM’s NEON and Intel’s MMX), thereby flexibly supporting different implementations. Low-power small-area CPUs can choose to implement shorter hardware vectors, while high-performance CPUs can opt for longer hardware vectors, and the same software code can be compatible across them.
3.16 Custom Instruction Extensions
In addition to the aforementioned modular instruction subsets’ extensibility and selectivity, the RISC-V architecture has another important feature: it supports third-party extensions. Users can extend their own instruction subsets; RISC-V has reserved a large amount of instruction encoding space for user custom extensions and has defined four Custom instructions available for user direct use, each with several bits of sub-encoding space reserved. Thus, users can directly use these four Custom instructions to extend dozens of custom instructions.
3.17 Summary and Comparison
Processor design technology has evolved over decades, and with the development of large-scale integrated circuit design technology up to today, it presents the following characteristics:
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As high-performance processors have very strong hardware scheduling capabilities and high clock frequencies, hardware design hopes the instruction set can be as organized and simple as possible, enabling processors to achieve higher clock frequencies and lower area.
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Ultra-low-power processors, primarily focused on IoT applications, are even more demanding regarding low power consumption and small area.
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Memory resources are now richer than those in early RISC processors.
All these factors have made many early RISC architecture design concepts (which were born based on the technological background of the time) unable to assist modern processor design today; instead, they have become burdensome shackles. Some features defined by early RISC architectures not only hinder the hardware design of high-performance processors but also impose unnecessary complexity on ultra-low-power processor hardware design.
Thanks to the latecomer advantage, the new RISC-V architecture can avoid all these known burdens while leveraging its advanced design philosophy to create a “modern” instruction set. This section summarizes its characteristics again in Table 2.
Table 2: Summary of RISC-V Instruction Set Architecture Characteristics
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