Understanding the Working Principles of Microcontrollers: A Comprehensive Guide

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The basic structure of a microcontroller includes six parts: Central Processing Unit (CPU), memory, timer/counter, input/output interfaces, interrupt control system, and clock circuit.

1. Basic Components

Central Processing Unit (CPU)

Includes the arithmetic logic unit and control unit, which are the core of the microcontroller. The arithmetic logic unit can perform various calculations, while the control unit coordinates the operation of different parts of the microcontroller.

Memory

Used to store programs and raw data.

Clock Circuit

The clock circuit generates control signals for the microcontroller to execute instructions strictly according to timing.

Timer/Counter: Implements timing or counting functions.

Input/Output Interfaces (I/O): Facilitate data transfer between the microcontroller and other devices.

Interrupt Control System: Responds to interrupt requests from interrupt sources.

2. Microcontroller Pins

Dual Inline Package (DIP)

Plastic Leaded Chip Carrier (PLCC)

Power Pins: VCC (Pin 40) and VSS (Pin 20) connect to the positive and negative terminals of the power supply respectively.

Clock Circuit Pins: The microcontroller requires clock pulse signals to work, connected through (Pin 18) and (Pin 19) to the oscillator circuit.

Control Signal Pins include the following four:

EA (Pin 31): When EA is high, it executes the ROM program from internal first, then external. When low, it only executes the external ROM program.

RST (Pin 9): When a high signal of more than two machine cycles is input, it resets the microcontroller, initializing it and re-executing the program.

ALE (Pin 30): Controls the time-sharing transmission of the lower 8 bits of address and data when accessing external memory and other peripherals.

PSEN (Pin 29): External program memory read selection signal.

There are a total of 32 parallel input/output pins:

PO Pins (Pins 39-32): Can be used as address/data bus ports or ordinary I/O ports.

P1 Pins (Pins 1-8): Generally used only as I/O ports.

P2 Pins (Pins 21-28): Can output the high 8 bits of the address when accessing external memory, and can also be used as ordinary I/O ports.

P3 Pins (Pins 10-17): Mainly used for their second function, but can also be used as ordinary I/O ports.

3. Parallel Input/Output

P0 Pin Circuit Structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

2 field effect transistors (FET).

1 multiplexer, 1 inverter, and 1 AND gate.

P0 Pin Working Principle – Used as Multiplexed Address/Data Bus

Output: When the control signal is 1, the hardware automatically switches the multiplexer MUX to connect to the inverter output, while enabling the AND gate.

1. When the output address/data information = 1, the AND gate output is 1, the upper field effect transistor conducts, and the lower field effect transistor is off, resulting in P0.x pin outputting 1.

2. When the output address/data information = 0, the upper field effect transistor is off, the lower field effect transistor conducts, resulting in P0.x pin outputting 0.

P0 Pin Working Principle – Used as Multiplexed Address/Data Bus

Input: When P0 is used as data input, it only reads information from external pins, with the control signal being 0, connecting the multiplexer to the latch Q terminal.

When P0 is accessed in multiplexed address/data mode to external memory, the CPU automatically writes FFH to P0, turning off the lower field effect transistor, while the upper field effect transistor is also off due to the control signal being 0, ensuring high impedance input for data information, with data directly entering the internal bus via P0.x pin through input buffer BUF2.

1. When the D latch is 1, the pin is 0, the lower field effect transistor is off, the output is open-drain, and a pull-up resistor must be connected externally to get a high-level output;

2. When the D latch is 0, the lower field effect transistor conducts, and P0 pin outputs low level.

P0 Pin Working Principle – Used as General I/O Pin

Input: Two reading methods: “Read Latch” and “Read Pin”.

1. When the CPU issues a “Read Latch” command, the state of the latch is entered into the internal bus via the upper tri-state buffer BUF1.

2. When the CPU issues a “Read Pin” command, the output state of the latch Q=1 (Q terminal is 0), causing the lower field effect transistor to turn off, and the pin state enters the internal bus via the lower tri-state buffer BUF2.

P1 Pin Circuit Structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

1 field effect transistor (FET) and 1 internal pull-up resistor.

P1 Pin Working Principle – Used Only as General I/O Pin

1. If the CPU outputs 1, Q=1, Q-=0, the field effect transistor is off, and P1.x pin outputs 1;

2. If the CPU outputs 0, Q=0, Q-=1, the field effect transistor conducts, and P1.x pin outputs 0.

P1 Pin Working Principle – Used Only as General I/O Pin

Input: Divided into “Read Latch” and “Read Pin”

1. Read “Latch”, the output Q state enters the internal bus via input buffer BUF1;

2. “Read Pin”, first write 1 to the latch, turning off the field effect transistor, the level on P1.x pin enters the internal bus via input buffer BUF2.

P2 Pin Circuit Structure

1 data output latch.

2 tri-state data input buffers BUF1 and BUF2.

1 field effect transistor (FET) and 1 internal pull-up resistor.

1 multiplexer MUX

P2 Pin Working Principle – Used as Address Bus

Under the control signal, the multiplexer connects to the “address”.

1. When the “address” is 0, the field effect transistor conducts, and the P2 pin outputs 0;

2. When the “address” line is 1, the field effect transistor is off, and the P2 pin outputs 1.

P2 Pin Working Principle – Used as General I/O Pin

Output: Under the internal control signal, the multiplexer connects to the latch Q terminal.

1. When the CPU outputs 1, Q=1, the field effect transistor is off, and P2.x pin outputs 1;

2. When the CPU outputs 0, Q=0, the field effect transistor conducts, and P2.x pin outputs 0.

P2 Pin Working Principle – Used as General I/O Pin

Input: Divided into two methods: “Read Latch” and “Read Pin”.

1. When “Read Latch”, the Q terminal signal enters the internal bus via input buffer BUF1;

2. When “Read Pin”, first write 1 to the latch, turning off the field effect transistor, the level on P2.x pin enters the internal bus via input buffer BUF2.

P3 Pin Circuit Structure

1 data output latch.

3 tri-state data input buffers BUF1 and BUF2.

1 field effect transistor (FET) and 1 internal pull-up resistor.

1 multiplexer MUX and 1 NAND gate

P3 Pin Working Principle – Used for Secondary Function

Output: The latch of this pin needs to be set to “1”, enabling the NAND gate.

When the second output is 1, the field effect transistor is off, and P3.x pin outputs 1;

When the second output is 0, the field effect transistor conducts, and P3.x pin outputs 0.

P3 Pin Working Principle – Used for Secondary Function

The latch of this pin and the second output function terminal must both be set to 1 to ensure the field effect transistor is off, and the information on P3.x pin is obtained from the output of input buffer BUF3.

P3 Pin Working Principle – Used as General I/O Pin

Output: The secondary output function terminal should remain “1”, enabling the NAND gate.

When the CPU outputs 1, Q=1, the field effect transistor is off, and P3.x pin outputs 1;

When the CPU outputs 0, Q=0, the field effect transistor conducts, and P3.x pin outputs 0.

P3 Pin Working Principle – Used as General I/O Pin

Input: The output latch of P3.x pin and the second output function must both be set to 1, ensuring the field effect transistor is off.

The information on P3.x pin enters the internal bus through input BUF3 and BUF2, completing the “Read Pin” operation;

It can also perform the “Read Latch” operation, at which point the Q terminal information enters the internal bus via buffer BUF1.

All four parallel ports (P0-P3) need to set the latch to “1” before reading the pins to ensure the field effect transistors are off, avoiding interference from data in the latch.

Since an additional preparation step of setting to “1” is required before input operations, they are referred to as “quasi-bidirectional ports”.

All four parallel ports (P0-P3) are quasi-bidirectional ports.

4. Minimum System Board of 8051 Microcontroller

The 8051 microcontroller has 4KB of flash memory, making it a minimal application system for digital input/output.

When constructing the minimum application system for 8051 microcontroller, it only requires an external clock circuit and reset circuit, as shown in the figure below.

Note: This minimum application system can only serve as a small-scale digital measurement and control unit.

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1. Basic Components

2. Microcontroller Pins

3. Parallel Input/Output

4. Minimum System Board of 8051 Microcontroller

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