1. Physical Layer:

The physical layer specifies the transmission medium, electrical characteristics, IO circuits, and synchronization mechanisms. In simple terms, it defines how the sender Tx obtains the encoded data from the upper layer, converts it into what kind of electrical signals, and sends it to the receiver Rx through how many channels and in what form.

The physical layers of CSI and DSI are defined by specialized working groups. Currently, there are three types of camera-based physical layer interfaces published: D-PHY, C-PHY, and M-PHY. Among them, the simplest and most widely used is the D-PHY interface, which was released in 2009 as D-PHY version 1.0.

To provide higher interface bandwidth and better channel layout flexibility, CSI-2 v1.3 introduced the C-PHY interface. C-PHY 1.0 is a new physical interface released by the MIPI Alliance in September 2014, which is compatible with the previous D-PHY v1.2 version.

D-PHY and C-PHY are both serial interfaces that solve many problems of parallel interfaces, such as reducing interface power consumption and improving the scalability issues of parallel interfaces. In addition to these two, there is also M-PHY, which is a high-speed Serdes interface with asynchronous transmission. Compared to D-PHY, it has fewer pins and higher signal transmission speed. While it is not as widely used in mobile applications, it is more commonly used in automotive applications, which will not be discussed in detail here.

2. Two Operating Modes of D-PHY:

The initial design goal of the first version of D-PHY was 500 Mbits/s, where D is the Roman numeral (Latin numeral) for 500, hence the name D-PHY. D-PHY is a high-speed, low-power source-synchronous physical layer, and due to its high efficiency design, it is very suitable for battery-powered devices with high power consumption. D-PHY contains both high-speed modules and low-power modules that help achieve high efficiency. Payload data (image data) uses high-speed modules, while control and status information transmission (between the camera/display and application processor) uses low-power modules (utilizing low-frequency signals). It has the unique ability to send high-speed and low-power data in a single data packet pulse. The low-power module helps save power, while the high-speed module helps meet the high bandwidth requirements for high-definition photo quality data signals.

The physical layer of D-PHY supports two transmission modes: HS (High Speed) and LP (Low Power), which use different transmission levels and mechanisms.

In HS mode, a source-synchronous transmission method is used, providing DDR clock from the master (Master) device to the slave (Slave) device. Differential signal transmission is used.

In LP mode, single-ended signal transmission is used, and the channels used for differential transmission in HS mode are split into two independent signal lines.

Whether in HS mode or LP mode, the transmission method is LSB first, MSB last. The combination of the two modes ensures that the MIPI bus can transmit large amounts of data (such as images) at high speed when needed, while reducing power consumption when large data transfers are not required.

3. Structure of Universal Lane:

The English meaning of Lane is “channel”, which we can understand here as the channel for completing information transport between two different modules.

Two chips connected by D-PHY are connected in the middle using differential signal pairs, with a Lane module at each transceiver end to complete data transmission and reception. The Lane module and the connecting line together constitute a complete data transmission channel, which is the core of the entire protocol’s physical layer. The following diagram shows a complete bidirectional data transmission Lane module (referred to as Universal Lane in MIPI), which is the basic information transmission unit of D-PHY.

Universal Lane consists of a pair of high-speed transceivers (HS-TX, HS-RX), a pair of low-power transceivers (LP-TX, LP-RX), a low-power competition detector (LP-CD), and Lane’s control logic. All transceiver modules share the same pair of differential lines Dp and Dn (which are two separate signal lines in LP mode). The entire Lane connects to other parts of the system through the PPI interface (PHY Protocol Interface).

双向：Bidirectional
单向：Unidirectional

Universal Lane supports bidirectional communication, while Lane that only requires unidirectional communication is simplified based on this. In systems that only require unidirectional communication, such as CSI, the host (generally fixed as Transmitter) does not need the RX module, and the slave (generally fixed as Receiver) does not need the TX module.

Additionally, even in bidirectional communication systems, the signal of the Clock Lane only needs to be sent from the host to the slave, and does not need to be transmitted in reverse. When data is sent from the slave to the host, the DDR clock is still provided by the host.

4. Three Operating Modes of Data Lane:

The three operating modes of the data lane are:

• Burst Mode: High-speed mode.

• Control Mode: Control mode in low-power mode.

• Escape Mode: Escape mode in low-power mode.

During normal operation, the data channel is in high-speed mode or control mode. Burst Mode and Escape Mode cannot be switched directly back and forth; they must be transferred through Control Mode, i.e.:

Burst Mode ↔ Control Mode ↔ Escape Mode

1. High-Speed Mode (Burst Mode)

High-speed mode is the mode under HS state, used to transmit images. In high-speed mode, the channel state is differential 0 or 1, meaning that when Dp is higher than Dn, it is defined as 1; when Dp is lower than Dn, it is defined as 0. The typical line voltage at this time is a differential of 200MV.

2. Control Mode

Control mode is a mode under LP state. The typical high level amplitude is 1.2V, at which point the signals on Dp and Dn are not differential signals but independent of each other. When Dp is 1.2V and Dn is also 1.2V, the MIPI protocol defines the state as LP11; when Dp is 1.2V and Dn is 0V, it defines the state as LP10, and so on. Control mode can form four different states: LP11, LP10, LP01, LP00.

The MIPI protocol stipulates that the four different states of control mode are composed of different sequences to represent entering or exiting a certain mode. For example, after the sequence LP11-LP01-LP00, it enters high-speed mode.

3. Escape Mode

Escape mode is a special operation of the data lane in LP state. In this mode, some additional functions can be entered: LPDT (Low Power Data Transmission Mode), ULPS (Ultra Low Power Mode), Trigger. Once entering Escape mode, the sender must send a single 8-bit command to respond to the requested action.

The data lane enters Escape mode through LP-11→LP-10→LP-00→LP-01→LP-00

Exiting Escape mode: LP-10→LP-11

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