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2025-01-26

Understanding the Basic Structure of CPLD and FPGA

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This article mainly introduces the basic structure of CPLD and FPGA.

CPLD stands for Complex Programmable Logic Device, and FPGA stands for Field Programmable Gate Array. Both have similar functions, and the programming process is also quite similar (the burning files are different, but they are automatically generated by software). The only difference is that the internal implementation principles and structures of the chips are slightly different.

CPLD

The CPLD mainly consists of programmable I/O units, basic logic units, wiring pools, and other auxiliary functional modules.

Understanding the Basic Structure of CPLD and FPGA

  • Programmable Logic Unit

It serves the same purpose as the basic I/O ports of FPGA, but the application range of CPLD is relatively limited. The performance and complexity of I/O are somewhat inferior compared to FPGA, supporting fewer I/O standards and lower frequencies.

  • Basic Logic Unit

The basic logic unit in CPLD is a macro unit. A macro unit is composed of AND/OR arrays plus flip-flops, where the AND/OR array completes the combinational logic function, and flip-flops are used to complete sequential logic.
Another important concept related to the basic logic unit of CPLD is the product term. A product term refers to the output of the AND array in the macro unit, and its quantity marks the capacity of the CPLD. The product term array is essentially an AND/OR array, where each intersection is a programmable fuse. If it is conductive, it implements the AND logic, and generally, there is an OR array after the AND array to complete the OR relationship in the minimal logic expression.

  • Wiring Pool, Wiring Matrix

The wiring resources in CPLD are much simpler than those in FPGA and are relatively limited, usually adopting a centralized wiring pool structure. The wiring pool is essentially a switch matrix that can connect the inputs and outputs of different macro units through knot points. Due to the lack of interconnection resources within CPLD devices, there may be difficulties in wiring in certain cases. Since the wiring pool structure of CPLD is fixed, the delay from input pins to output pins is also fixed, referred to as Pin to Pin delay, represented by Tpd. The Tpd delay reflects the maximum frequency that CPLD devices can achieve, clearly indicating the speed grade of CPLD devices.

FPGA

FPGA consists of six parts: programmable input/output units, basic programmable logic units, embedded block RAM, rich wiring resources, underlying embedded functional units, and embedded dedicated hard cores.

Understanding the Basic Structure of CPLD and FPGA

  • Programmable Input/Output Unit (IOB)

The programmable input/output unit is the interface part between the chip and external circuits, fulfilling the driving and matching requirements for input/output signals under different electrical characteristics. The I/O inside FPGA is classified into groups, and each group can independently support different I/O standards. Through flexible software configuration, it can adapt to different electrical standards and I/O physical characteristics, adjust matching impedance characteristics, change pull-up and pull-down resistors, and adjust drive current size.External input signals can be input to the internal FPGA through the storage unit of the IOB module or directly input into the FPGA. When external input signals are input into the FPGA through the storage unit of the IOB module, the hold time requirement can be reduced, usually defaulting to 0.
To facilitate management and adapt to various electrical standards, the IOB of FPGA is divided into several groups (banks), where the interface standard of each bank is determined by its interface voltage VCCO. Only one VCCO can exist in one bank, but different banks can have different VCCO. Only ports with the same electrical standard can be connected together, and the same VCCO voltage is a basic condition for the interface standard.

  • Basic Programmable Logic Unit

The basic programmable logic unit of FPGA is composed of lookup tables (LUT) and registers. The lookup table completes pure combinational logic functions. The internal registers of FPGA can be configured as flip-flops with synchronous/asynchronous reset and enable, or it can be configured as latches. FPGA generally relies on registers to complete synchronous timing logic design. Generally speaking, a classic configuration of the basic programmable unit is one register plus one lookup table, but the internal structure of registers and lookup tables varies among different manufacturers, and the combination patterns of registers and lookup tables also differ.
Understanding the LUT and Register ratio of the underlying configuration unit is significant for device selection and scale estimation. In addition to the basic programmable logic unit, FPGA also has embedded RAM, PLL or DLL, and dedicated Hard IP Core, which can equivalently represent a certain scale of system gates. Therefore, a simple and scientific method is to measure the number of registers or LUTs in the device.

  • Embedded Block RAM

Most FPGA devices currently have embedded block RAM. Embedded block RAM can be configured as single-port RAM, dual-port RAM, content addressable memory (CAM), and FIFO, among other common storage structures.
CAM, or content addressable memory, compares the data written to it with every piece of data stored inside and returns the addresses of all internal data that are the same as the port data. In simple terms, RAM is a storage unit that writes addresses and reads data; CAM is the opposite of RAM.
Besides block RAM, Xilinx and Lattice’s FPGAs can also flexibly configure LUTs as RAM, ROM, FIFO, and other storage structures.

  • Rich Wiring Resources

The wiring resources connect all internal units of FPGA, and the length and process of the wires determine the driving capability and transmission speed of signals on the wires. They are classified into four different categories based on process, length, width, and distribution location:

  • Global dedicated wiring resources: used for routing global clock and global reset/set signals within the chip;

  • Long line resources: used for routing some high-speed signals and secondary global clock signals between device Banks;

  • Short line resources: used for completing logic interconnections and wiring between basic logic units;

  • Others: various wiring resources and dedicated control signal lines such as clocks and resets are available inside the logic units.

During the design process, the layout router often automatically selects available wiring resources to connect the used underlying unit modules based on the topology of the input logic netlist and constraints, so the wiring resources are often overlooked. However, the optimization and usage of wiring resources are directly related to the implementation results.

  • Underlying Embedded Functional Units

The embedded functional modules mainly refer to DLL (Delay Locked Loop), PLL (Phase Locked Loop), DSP, and CPU soft cores. The increasingly rich embedded functional units make single-chip FPGA a system-level design tool, enabling it to have the capability for co-design of hardware and software, gradually transitioning to SOC platforms.
DLL and PLL have similar functions, completing high-precision, low-jitter clock multiplication and division, as well as duty cycle adjustment and phase shifting functions. Chips produced by Xilinx integrate DLL, while Altera’s chips integrate PLL, and Lattice’s new chips integrate both PLL and DLL.

PLL and DLL can be easily managed and configured through tools generated by IP cores.

  • Embedded Dedicated Hard Cores

These are different from the “underlying embedded units”; the hard cores referred to here are mainly those with relatively weak universality and are not included in all FPGA devices.
Embedded dedicated hard cores are compared to the underlying embedded soft cores, referring to hard cores (Hard Core) with powerful processing capabilities of FPGA, equivalent to ASIC circuits. To enhance FPGA performance, chip manufacturers integrate some specialized hard cores inside the chips.For example:To improve the multiplication speed of FPGA, mainstream FPGAs integrate dedicated multipliers; to adapt to communication bus and interface standards, many high-end FPGAs integrate serial/parallel transceivers (SERDES) that can achieve transmission speeds of tens of Gbps.
Xilinx’s high-end products not only integrate ARM but also embed DSP Core modules, proposing concepts such as MPSoC and RFSoC.
The next article will introduce the differences between CPLD and FPGA.
Understanding the Basic Structure of CPLD and FPGA

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Understanding the Basic Structure of CPLD and FPGA

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Understanding the Basic Structure of CPLD and FPGA

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Understanding the Basic Structure of CPLD and FPGA

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Understanding the Basic Structure of CPLD and FPGA

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