As a hardware engineer, we often deal with microcontrollers (MCUs). However, when selecting an MCU, in addition to pin functions, we should be more familiar with the three important parameters: Flash, EEPROM, and SRAM. If we do not prepare adequately in advance, we may find ourselves wasting more time and effort later on when we discover that our initial choice was inappropriate. Don’t ask why; these are lessons learned through blood and tears. Today, let’s discuss the differences among these three types of memory to make our MCU selection process more straightforward.1. Functions of the Three Types
| Memory Type | Core Function | Failure Consequence | Capacity Requirement Scenario |
| Flash | Store program code + constant data | Cannot start / Function abnormal | Complex OS / Algorithms (e.g., OpenCV) |
| SRAM | Store runtime variables / Stack / Cache | Data loss / Stack overflow crash | Multitasking / Large data buffering |
| EEPROM | Store user parameters / Calibration data (frequent modifications) | Configuration loss / Operating point shift | Calibration data that needs to be retained during power loss |
2. In-depth Comparison of Memory Physical Characteristics
| Parameter | Flash | SRAM | EEPROM |
| Read/Write Speed | 70ns (read) / 500μs (write) | 5ns (zero latency) | 100ns (read) / 5ms (write) |
| Erase/Write Lifespan | 100,000 to 1,000,000 times (NOR Flash) | ∞ | 1,000,000 times |
| Power Consumption (Write Operation) | 15mA (requires high voltage pump) | 20mA (full-speed operation) | 5mA (byte write) |
| Cell Area | Small (high density) | Large (6T structure occupies 70% of silicon area) | Largest (special process) |
3. Memory Capacity Selection1. Flash Selection Principles Minimum redundancy: actual code size * 1.5 (reserve space for OTA upgrades) Example: actual code = 128KB Recommended capacity = 128 * 1.5 = 192KB → choose 256KB model Critical value warning: ≤32KB: cannot run lightweight RTOS (e.g., FreeRTOS requires 40KB+) ≥1MB: startup time extended (e.g., STM32H7 loading requires 100ms)2. SRAM Selection // Safe capacity calculation in RTOS environment #define MIN_RAM = (task stack * number of tasks) + (message queue buffer) + global variables + safety margin Task stack: 2KB*5 tasks = 10KB Message queue: 3KB Global variables: 5KB Safety margin (30%): 5.4KB Total ≥ 23.4KB → choose 32KB 3. EEPROM Selection Strategy
| Data Characteristics | Recommended Solution |
| Parameter < 512B, few writes | Flash emulation (save $0.1 cost) |
| Parameter > 2KB, frequent writes | External EEPROM chip (e.g., AT24C256) |
| Extreme durability requirements | FRAM (ferroelectric) alternative |
Life trap: When emulating EEPROM with Flash, repeatedly erasing the same sector will lead to premature damage of the block!4. Optimal Selection Recommendation Table (Microcontroller)
| Application Scenario | Recommended Model | Flash | SRAM | EEPROM | Key Technical Points |
| Consumer Electronics Remote Control | STM32G030 | 64KB | 8KB | Flash emulation | Cost-performance king |
| Industrial HMI | GD32E507 | 512KB | 128KB | 6KB independent | Hardware encryption + wide temperature |
| IoT Gateway | ESP32-S3 | 1MB (SPI) | 512KB | External expansion | Dual-core + WiFi6 |
| Automotive Sensor | Renesas RA6M4 | 2MB | 512KB | 64KB FRAM | ASIL-D functional safety |
5. Case Analysis of Mistakes1. Shared Bicycle Lock Scheme Incorrect configuration: 64KB Flash + 4KB SRAM Failure phenomenon: GPS data accumulation leads to stack overflow Root cause: 4KB SRAM cannot buffer base station communication frames (requires ≥6KB) Fix: Upgrade to 8KB SRAM model2. Industrial Temperature Controller Failure Event Incorrect configuration: using Flash to store temperature calibration parameters (writing 30 times daily) Failure phenomenon: after 1 year, temperature value shifts ±5℃ Failure mechanism: Flash lifespan of 10,000 times exhausted Solution: switch to EEPROM storage (lifespan increased by 100 times)6. Conclusion:Memory selection is not about being larger but about precisely matching needs + redundancy design• Flash capacity = code size × 1.5 + OTA firmware space• SRAM capacity = (peak data + stack depth) × number of tasks × 1.3• EEPROM = parameter quantity × 2 (durability requirements determine the technical path)Cost control rule: prioritize SRAM, followed by Flash, and expand EEPROM as needed.