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1. Concept of Address Translation
The code in ARMV8-A generally uses virtual addresses for addressing access, which are converted into physical addresses in the memory system. This conversion is performed by a component of the processor called the MMU. The MMU uses a translation table to convert virtual addresses to physical addresses; this translation table is also known as the page table and is stored in the system’s memory. The MMU automatically reads the contents of the translation table (page table) when necessary; this reading action is referred to as a Table Walk.
One important function of the MMU is to introduce virtual memory functionality, allowing the system to support multiple processes, where each process operates as if it is running in its own private virtual memory space. Each process can run in a segment of virtual memory with the same virtual address value. Processes are unaware of each other’s existence and do not need to know how much physical memory there is or how it is laid out. Even if physical memory is discrete, the MMU can map physical memory to a continuous virtual address space in virtual memory. We can read, write, compile, and link applications in virtual memory. Therefore, once the MMU is enabled, virtual addresses are generally used by users, compilers, and linkers; physical addresses are used by the actual hardware. The MMU uses the highest two bytes (16 bits) to differentiate which page table base register to select. ARMV8-A has two page table base registers: TTBR0_EL1 and TTBR1_EL1. When designing the operating system kernel, if the high bits of the virtual address (bits 48-63) are all 1s (i.e., 0xffff0000_00000000 to 0xffffffff_ffffffff), TTBR1_EL1 is selected; when the high bits are all 0s (i.e., 0x0 to 0x0000ffff_ffffffff), TTBR0_EL1 is selected. The following figure is an example of the usage of the TTBR0_EL1 and TTBR1_EL1 registers:
Additionally, because virtual addresses require the MMU for address translation, the MMU can also apply permission controls to virtual addresses, such as read/write executable access permissions, memory ordering, and cache policies.
2. Address Isolation Between Kernel and Applications
Operating systems generally run multiple processes simultaneously, and each process has its own unique set of page tables. During context switching between processes, the page table is one of the contents that need to be switched. In most cases, the high-address memory is primarily used by the kernel, and the contents of the page table that record the mapping relationship from virtual addresses to physical addresses rarely change. The ARMV8-A architecture provides several features to improve the efficiency of context switching.
The base address of the page table is specified by the registers TTBR0_EL1 and TTBR1_EL1, as shown in Figure 1. TTBR0_EL1 stores the page table base address for user-mode processes, while TTBR1_EL1 stores the page table base address for the kernel. The operating system uses these two different page table base registers to differentiate and isolate user-mode virtual addresses from kernel-mode virtual addresses.
It is worth noting that EL2 and EL3 only have the TTBR0 register and do not have TTBR1. This means that the virtual address space addressing range for EL2 and EL3 is 0x0 to 0x0000ffff_ffffffff.
The page table translation control register TCR_EL1 provides address check bits T0SZ[5:0] and T1SZ[5:0]. They define the minimum and maximum values of the virtual address range and determine the granularity of a page of the page table and the starting level of the page table. The bit definitions of the TCR_EL1 register are shown in Figure 2.
Among them, TG1, T1SZ, TG0, and T0SZ control the page granularity size and virtual address size; the IPS size controls the size of the IPA address space (in virtualization scenarios). In short, TCR_EL1 controls the memory management features of EL1 and EL0.
For more information, please read “Introduction to MMU in ARMV8-A – Part 2”.
