When it comes to the design and energy efficiency of processors, if we talk about the most classic RISC processor, then it must be MIPS. Even its competitors have to acknowledge its elegance. It is regarded as a model in processor textbooks, and many other processors bear its influence. Next, let’s explore the origins of MIPS architecture and its evolution in China.
Origins:MIPS architecture has a long history
In 1981, Stanford University professor John Hennessy led his team to develop the first MIPS architecture processor.MIPS stands for “Microprocessor without interlocked piped stages,” and its mechanism aims to utilize software methods to avoid data dependency issues in the pipeline.
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In 1984, Professor John Hennessy left Stanford University to found MIPS Computer Systems.
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In 1986, MIPS launched the R2000 processor.
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In 1988, the R3000 processor was launched.
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In 1991, the first commercial 64-bit microprocessor R4000 was released.
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In 1994, the R8000 processor was released.
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In 1996, the R10000 processor was released.
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In 1997, the R12000 processor was released.
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In 1999, MIPS announced the MIPS 32 and MIPS 64 architecture standards.
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In 2000, MIPS released a new version for MIPS 32 4Kc and the future 64-bit MIPS 64 20Kc processor cores. MIPS architecture developed rapidly after 2010, releasing 4 versions in 5 years until 2014.
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In 1992, SGI acquired MIPS Computer Systems.
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In 1998, MIPS separated from SGI and became MIPS Technologies; subsequently, MIPS shifted its focus to embedded systems.
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In 1998, MIPS Technologies went public on the NASDAQ stock exchange.
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In 1999, MIPS released the MIPS32 and MIPS64 architecture standards, laying the foundation for future MIPS processor development. The new architecture integrated all original NIPS instruction sets and added many more powerful features. MIPS developed high-performance, low-power 32-bit processor cores (core) MIPS324Kc and high-performance 64-bit processor cores MIPS64 5Kc.
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In 2000, MIPS released versions for MIPS32 4Kc and 64-bit MIPS 64 20Kc processor cores.
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On August 16, 2007, MIPS Technologies announced that the Loongson Central Processing Unit from the Institute of Computing Technology, Chinese Academy of Sciences, obtained all patents and licenses for its processor IP and bus, instruction set.
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On December 20, 2007, MIPS Technologies announced that Yangzhi Technology had obtained authorization for its customizable system-on-chip (SoC) core “MIPS32 24KEc Pro” designed for advanced multimedia.
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In 2012, MIPS Technologies was acquired by Arm and Imagination, and later Imagination was acquired by Canyon Bridge, with MIPS subsequently taken over by Tallwood Venture Capital. Later, the startup Wave Computing took over MIPS from Tallwood.
During the development of the MIPS instruction set, it has largely maintained backward compatibility with new versions. For example, MIPS Release 5 can be backward compatible with all previous instruction set versions. However, this changed with MIPS Release 6, which introduced new instructions, simplified the instruction set, removed some rarely used instructions, and rearranged the instruction encoding, freeing up a large number of instruction slots for future expansion. Therefore, MIPS Release 6 can be seen as an almost entirely new definition.
1. MIPS I
Provides load/store, computation, jump, branch, co-processing, and other special instructions. This instruction set architecture was used for the initial MIPS processors R2000/R3000. R2000 was the first MIPS CPU launched in 1985, consisting of 110,000 transistors, and is an 8MHz 32-bit processor. R3000 is the next generation product of R2000, differing only in clock frequency.
2. MIPS II
Added self-trap instructions, link load instructions, conditional store instructions, synchronization instructions, possible branch instructions, and square root instructions. Initially planned for the MIPS processor R6000, but due to process selection issues, R6000 faced continuous problems since its design began in 1988 and ultimately failed to be mass-produced. However, MIPS II instruction set architecture is the direct predecessor of the later MIPS32 instruction set architecture.
3. MIPS III
Provided a 32-bit instruction set while supporting a 64-bit instruction set simultaneously. Initially used in the MIPS processor R4000, which was launched in 1991 as the first 64-bit processor, adding a floating-point processing unit for the first time and increasing the main clock frequency to 100MHz. Later, a series of R4000 processors were released.
4. MIPS IV
Added conditional move instructions, prefetch instructions, and some floating-point instructions based on MIPS III. Initially used in the MIPS processor R8000, later applied to R5000/R10000. MIPS IV added features to improve instruction-level parallelism and introduced several new FP arithmetic instructions for single and double precision FPN.
5. MIPS V
Added instructions to improve code production efficiency and data transfer efficiency based on MIPS IV. However, no processor was based on this architecture. MIPS V instruction set architecture is the direct predecessor of the later MIPS64 instruction set architecture.
6. MIPS32/64
MIPS32/64 was proposed in 1998, with MIPS32 based on MIPS II architecture, selectively adding MIPS III, MIPS IV, and MIPS V to improve code generation and data movement efficiency. MIPS64 is based on MIPS V architecture and is compatible with MIPS32.
7. microMIPS32/64
The microMIPS32/64 instruction set architecture integrates high-performance code compression technology for 16-bit and 32-bit optimized instructions, maintaining 98% of MIPS32 performance while reducing code size by at least 30%, thereby reducing chip costs and helping to reduce system power consumption.
8. nano MIPS architecture
Nano MIPS is designed specifically for embedded devices and is a variable-length instruction set architecture (ISA) that provides high performance while significantly reducing code size, delivering up to 40% less code compared to MIPS32.
Pros and Cons:MIPS Has Its Strengths and Weaknesses
The MIPS processor was a major focus of RISC CPU design in the mid-1980s. Semiconductor companies like Pace MIPS, IDT, and Toshiba adopted MIPS designs to manufacture chips, and their chips were used in terminals such as Sony and Nintendo game consoles, Cisco routers, and SGI supercomputers. Especially in the home router market, out of the more than 16 billion microprocessors produced each year, 99% are RISC processors. It was also used as a high-performance computing architecture in supercomputing platforms.
Compared to Intel, MIPS licensing fees are relatively low, making it adopted by most chip manufacturers other than Intel. In addition to the lower costs, MIPS has been popular for nearly 40 years for two reasons:
First, MIPS architecture licensing does not restrict any changes to the MIPS architecture.For example, Loongson initially used a nearly unchanged MIPS architecture, but began to autonomously extend the instruction set starting from Loongson 2. The early models of Loongson 3 were based on MIPS64 R3, but through continuous instruction set expansion, they formed the current LoongISA instruction set, which has now expanded from the initial 400 instructions to over 1000. Therefore, we can say that Loongson 3 is no longer a MIPS architecture, but it remains compatible with the MIPS64 R3 instruction set. However, Loongson’s LoongISA only supports up to MIPS64 R2/R3 and is not compatible with MIPS 64 R5/R6.
Secondly, MIPS belongs to the Reduced Instruction Set Computing (RISC) architecture, which, compared to the Complex Instruction Set Computing (CISC) architecture used by Intel, has advantages such as simpler design and shorter design cycles, allowing for more advanced technologies to be applied and faster development of the next generation of processors.
Everything has its opposite,MIPS architecture also has its own disadvantages – it needs to build its own ecosystem.MIPS licensing is divided into two categories: core licensing (Core License) and architecture licensing (Architecture License), with core licensing also known as IP licensing. MIPS’s pricing strategy is that core licensing is expensive while architecture licensing is cheap. Companies with the capability can use the MIPS instruction set to develop their own CPUs and can expand the instruction set without restrictions.
This model caused a flourishing effect in the short term, but in the long term, allowing for self-expansion of instructions led to ecological fragmentation and incompatibility, affecting the enthusiasm of developers and users. Additionally, due to poor management of MIPS in later years, the slow transition of architecture and failure to align with mainstream operating systems and device ecosystem optimization trends resulted in a loss of the rapid launch speed and high software compatibility that IP licensing provides. As a result, MIPS experienced a decline from 2007 to 2017 and gradually became marginalized.
Embracing Open Source:MIPS’s Future May Be More Open
However, in December 2018, MIPS welcomed another wave of attention. The American AI company Wave Computing, which once acquired MIPS, announced a significant news: the official launch of the MIPS Open project, making the MIPS architecture completely open source and free for global developers, partners, research institutions, and customers. This is a major initiative to promote the MIPS core and ecosystem, opening the ISA instruction set, and may become a balancing point for development and revenue.
Subsequently, the Wave website began to provide MIPS open-source related instruction sets and tools, including 32-bit and 64-bit MIPS R6 instruction sets, MIPS SIMD extensions, MIPS DSP extensions, MIPS Multi-Threading (MT), MIPS MCU, microMIPS architecture, MIPS Virtualization (VZ), and more. This means“In the future, anyone can freely access the above resources without any licensing or copyright fees and will be protected by hundreds of patents globally.”
Rupert Baines, CEO of UltraSoC, stated: “Considering the momentum of RISC-V development, MIPS’s move towards open source is a noteworthy and smart strategy.” He said: “MIPS already has a wealth of quality tools and software environments. This is a smart way to amplify MIPS’s advantages without losing too much.”
However, reports indicate that starting November 14, 2019, Wave will no longer provide downloads of MIPS open components including MIPS architecture, cores, tools, IDEs, simulators, and FPGA packages. The email emphasized that previous collaborations would not be affected, but Wave would no longer authorize any third-party certifications.
It seems that MIPS’s open-source path is not smooth, but open source is a necessary path for ecosystem construction. The road to open source is difficult and long; in the future, where will MIPS go? We shall wait and see…
The Evolution of MIPS in China
Companies in China that have obtained MIPS licenses include Loongson, Junzheng, and Zhuhai Juhua. Among them, we are more familiar with Loongson and Junzheng.Loongson follows a high-performance route, targeting clients in desktop, servers, scientific computing, etc.Junzheng focuses on low power consumption and customization, targeting niche markets.
Loongson
When discussing the evolution of MIPS in China, one must mention Loongson. Loongson bought out the MIPS architecture and based on MIPS, designed its own instruction set. In 2001, the Institute of Computing Technology, Chinese Academy of Sciences, began developing the Loongson processor. In 2002, the Loongson 1 was successfully taped out; in 2003, the Loongson 2B was successfully taped out; in 2004, the Loongson 2C was successfully taped out; in 2006, the Loongson 2E was successfully taped out; in 2007, the Loongson 2F was successfully taped out, which was the first product chip of Loongson; in 2009, the Loongson 3A was successfully taped out. In 2010, the Chinese Academy of Sciences and the Beijing Municipal Government jointly funded the establishment of Loongson Zhongke Technology Co., Ltd. Over the years, Loongson has evolved into new processors such as Loongson 2H/2J, 3A3000/B3000, and 3A4000/B4000.
In December 2019, Loongson released the latest models of the Loongson 3 series, 3A4000/3B4000. The 3A4000 is a significant upgrade over the 3A3000, adopting a 28nm process, doubling performance compared to the 3A3000, increasing the main frequency to 1.8GHz-2.0GHz, upgrading memory to DDR4 interface, and supporting dynamic frequency scaling, which can greatly extend the battery life of laptops.According to internal sources, the Loongson 3A5000 is under development and is expected to tape out successfully by the end of the second quarter of 2020.It is worth mentioning that Loongson has been autonomously expanding its instruction set since the second generation; currently, Loongson has customized its instruction set from the initial 400 instructions to over 1000.
In addition, while continuously improving product performance, Loongson has tirelessly built an independent and open Loongson ecosystem over the years, including developing on social software and giving back to open source, and collaborating with domestic manufacturers to launch various solutions, hoping to gather more partners to jointly promote the development of domestic CPUs.
Junzheng
Beijing Junzheng was established in July 2005 and is an integrated circuit design company focused on 32-bit embedded low-power CPU technology. Its team comes from Ark Technology and has continued the development direction of Ark Technology, emphasizing independent R&D of CPU cores.
Beijing Junzheng developed the XBurst CPU based on the MIPS architecture. The company has developed a low-power demand in the IoT, smart wearables, and smart home markets, relying on its self-developed low-power XBurst CPU. In 2017, Beijing Junzheng completed the design of XBurst2, and the company has been continuously optimizing it based on the XBurst2 CPU. The XBurst CPU adopts MIPS architecture and RISC technology, focusing on low power consumption. Under the same process, the XBurst’s computational performance increased by 80%, power consumption decreased by 70%, and chip size reduced by 50%.Beijing Junzheng has a competitive advantage in the smart home, smart wearable, and consumer smart camera markets due to its CPU technology advantages in portable consumer electronics and portable educational electronics.
Xilinx
Xilinx obtained exclusive operating rights for the MIPS architecture and CPU cores in China from Wave Computing at the end of 2018. Xilinx focuses on one-stop design services related to SoC and has rich experience in IoT, AI, and communications.
Zhuhai Juhua
Zhuhai Juhua is one of the world’s leading suppliers of personal portable multimedia SoCs. It has subsidiaries such as Juchip (Zhuhai) Technology Co., Ltd., Juhua Microelectronics (Shenzhen) Co., Ltd., and Hefei Juchip Intelligent Technology Co., Ltd. Among them, Juchip is a well-known low-power consumer system-on-chip design manufacturer in China, providing professional chips and complete solutions for wireless audio and smart ear-wear, smart multimedia, smart computing, and IoT products.
References:
[1] The MIPS open-source project has been terminated! http://www.360doc.com/content/19/1117/14/37805727_873716837.shtml
[2] The MIPS instruction set is open-sourced, with 32-bit and 64-bit architectures available for free.
https://baijiahao.baidu.com/s?id=1629583201518503416&wfr=spider&for=pc [3] Where is MIPS headed?
https://tech.sina.com.cn/roll/2019-12-17/doc-iihnzahi8061427.shtml
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Author:泥石流
Source:自主可控新鲜事(ID:ZZKK-IT)
