1. Overview
This project designs a simple digital clock based on the Orange Moon FPGA development board, displaying the day of the week, hours, minutes, and seconds on an OLED display. The onboard four buttons allow for incrementing the day, hours, and minutes, as well as decrementing the minutes. Additionally, the LED will blink to indicate the hour when it approaches the full hour.
This project references the open-source project “OLED Digital Clock” from the WeChat public account “FPGA Journey” and modifies the content from the previous article in this account titled “IIC OLED Character Display System Based on FPGA”. Modifications include adding a custom digital clock timing module and altering the state machine transition logic, allowing for initialization and reset operations to be performed sequentially upon power-up, leading to the digital clock display interface.
2. Experimental Platform Setup
The overall connection of this system is shown in Figure 1, where the OLED module is directly plugged into the FPGA development board, which drives the display through the IIC interface.
The main control chip is Intel’s Cyclone IV E series FPGA, specifically the EP4CE6E22C8N model. This chip features 6,272 logic elements, 270 kbits of embedded memory, and 2 general-purpose PLLs, providing abundant logic resources. The development board includes a camera interface, VGA interface, and SDRAM chip, making it a cost-effective image processing development board, also equipped with buttons, LEDs, and an OLED module, suitable for various logic designs.
Figure 1 Overall Connection Diagram
The OLED module used in this experiment is a 0.96-inch blue OLED 4P module, controlled via the IIC interface, with a resolution of 128*64, powered by 3.3V (5V power supply is also acceptable). The internal driver chip of the OLED screen is SSD1306.
3. Key Module Introduction
The following introduces the key modules of this experiment:
(1) IIC Bus Driver Module (I2C_Master.v): Implements the IIC bus protocol, directly controlling external IIC OLED devices.
(2) Initialization Module (Oled_Init.v): Writes commands to specific registers in the OLED display via the IIC interface to complete the OLED initialization.
(3) Screen Clear Module (Oled_Clear.v): After initialization, the data displayed on the OLED is chaotic; this module writes 0 to each column of the 8 pages of the OLED to clear the screen.
(4) Display Control Module (Oled_DClock_control.v): This module outputs the x and y coordinates of the characters to be displayed and the character index for subsequent character display. If character display needs to be modified, the number of characters and their corresponding x and y coordinates in this module must be changed.
(5) Character Display Module (Oled_DClock_Info.v): This module instantiates character data sub-modules, primarily responsible for reading character data from the sub-modules based on the x and y coordinates and character index from the display control module, writing it to the OLED via IIC to complete the corresponding character display.
(6) Character Data Module (DClock_font_data.v): Internally stores the corresponding character pattern data generated by the font generation software. If the characters to be displayed need to be modified, this module must also be updated accordingly.
(7) 1s Counting Module (clock_divide.v): This module uses a counter to count the 50MHz system clock for 1 second, generating a high-level pulse signal for one clock cycle every second, used for subsequent digital clock counting.
(8) Timing Module (clock_timer.v): The core timing module of the digital clock, with inputs including debounced flag signals from four time-setting buttons and the 1s counting flag signal, and outputs the day of the week, high and low bits of the hour, high and low bits of the minute, and high and low bits of the second.
(9) Key Debounce Module (key_filter.v): This module implements key debounce functionality, ensuring that each press of a button outputs a high-level pulse signal for one clock cycle.
4. Experimental Verification
The pin binding results of this project are shown in Figure 2.
Figure 2 Pin Binding
The RTL view of this project is shown in Figure 3.
Figure 3 RTL View
The summary interface after compilation of this project is shown in Figure 4.
Figure 4 Project Summary Interface
Finally, the compiled sof file is downloaded to the FPGA development board, and the OLED display result is shown in Figure 5.
Figure 5 Digital Clock Display Result
Descriptions of various peripheral functions are shown in Figure 6, which include day adjustment, hour adjustment, minute adjustment, and hourly chime functionality.
Figure 6 Peripheral Function Descriptions
5. Code Acquisition
Follow the WeChat public account “Learning FPGA with Electrical Xiaoxing” and reply in the background: OLED Digital Clock
Contact Information:
QQ: 2475990849
WeChat: lx17863151922