Click to follow for more exciting content!!
01PARTIntroduction
This article provides a brief explanation of the usage of BSCAN based on the Spartan-6 and Kintex-7 series of FPGAs, using the K735 development board and LS-Extended development board; the software used includes riscv-openocd and riscv-gdb (included in the toolchain).
Principle Explanation02PART
BSCAN stands for JTAG-boundary-scan, which is a serial interface with a four-port JTAG timing used to test the circuit logic of large integrated circuits. Its advantages include the following:
1. Testing of logic circuits can be performed without adding extra pins.
2. Quick testing of connections to peripheral devices can be done without embedded software.
3. It can program the flash of microcontrollers.
OpenOCD (Open On-Chip Debugger) is an open-source on-chip debugger initially initiated by Dominic Rath during his university days (2005). OpenOCD aims to provide debugging, system programming, and boundary scan capabilities for embedded devices.
The process of BSCAN reusing JTAG is as follows:
First, OpenOCD writes USER4 to the TAP’s IR of the FPGA via JTAG (USER4 is the default channel, which can be set to USER1, USER2, and other custom channels, but the corresponding code in OpenOCD needs to be modified). Then, it writes specific formatted data to the DR; subsequently, the BSCAN IP will be responsible for parsing the data from the DR and controlling the processor’s JTAG based on the DR data.
In simple terms, it encapsulates the data from the DR and passes it to BSCAN to parse the corresponding data content, and then controls the processor’s JTAG based on the data content.
Hardware Implementation
Before Modification: Processor TAP directly connected to TAP
After Modification: Processor and FPGA reuse a JTAG Header
Software Implementation
The original code has implemented the usage of BSCAN for the Xilinx 7 series, but due to some differences in the BSCAN primitives between Spartan-6 and the 7 series, I added a command and modified the corresponding code in riscv-openocd to also support the usage of BSCAN for Spartan-6. The code has been open-sourced on GitHub; click the link below to read the original text.
OpenOCD Run Result
03PARTResult Display
Initially, GPIO was directly connected to the FT2232 module, and then connected to the host computer for programming and debugging. The Dupont wires were messy and occupied some GPIOs.
Now, the FPGA’s JTAG can be reused, and programming the bitstream, downloading programs, and debugging all share one interface, freeing up some GPIOs and eliminating messy Dupont wires.
